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| INTEGRATED CIRCUITS DATA SHEET P83CL882 80C51 Ultra Low Power (ULP) telephony controller Product specification File under Integrated Circuits, IC22 2001 Jun 19 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller CONTENTS 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 8 8.1 8.2 8.3 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pin configuration Pin description FUNCTIONAL DESCRIPTION Oscillator circuitry The CPU Interrupt controller Port control logic Timer 0 and Timer 1 event counters Timer 2 Watchdog Timer I2C-bus serial I/O (master/slave interface) MSK modem Internal Data Memory Special Function Registers overview INSTRUCTION SET Instruction map APPLICATION INFORMATION Introduction Differences between P83CL882 and the Metalink EH emulation system The asynchronous handshake CPU 9 9.1 9.2 9.3 10 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 P83CL882 HOW TO ESTIMATE P83CL882 POWER CONSUMPTION General Modes Examples of power consumption estimation LIMITING VALUES CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2001 Jun 19 2 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 1 FEATURES P83CL882 * Full static asynchronous handshake 80C51 CPU; enhanced 8-bit architecture with: - Standard 80C51 instruction set - CPU speed independent of clock frequency, average speed: 4.8 Mips at 3.0 V - Non-page oriented instructions - Direct addressing - Four 8-byte RAM register banks - Stack depth limited only by available internal RAM (maximum 128 bytes) - Multiply, divide, subtract and compare instructions. * 17 source, 17 vector interrupt structure with two priority levels, polarity and sensitivity choice * 24 general purpose I/O pins * Timer 0 and 1: two standard 16-bit timer/event counters * Timer 2: 16-bit timer/event counter with capture, compare and auto-reload function * Watchdog Timer * Wake-up counter * Idle and Power-down modes * 4-kbyte ROM: mask programmed read only memory * Supply voltage: 1.8 to 3.6 V * 128 bytes RAM * Internal crystal oscillator * Reset I/O pin for external reset from master or to slave * MSK modem including Manchester encoder/decoder with 2 digital outputs (by SW) for analog cordless telephones (standards CT0/CT1/CT1+) * I2C-bus master/slave (transmitter/receiver, maximum frequency 400 kHz). 2 GENERAL DESCRIPTION The P83CL882 is manufactured in an advanced CMOS technology. The P83CL882 is a member of the VTELX family of low-power, low-voltage 80CL51 microcontrollers with advanced features for telecom applications. The Philips exclusive, asynchronous handshaking technology has been used for the CPU implementation which makes the CPU to run at its maximum speed independent of the used crystal frequency. The P83CL882 is especially suited for low cost analog cordless telephone applications (CT0, CT1 and CT1+ standards) and wired feature phones. For this purpose, functions like MSK modem and I2C-bus are integrated on-chip. The device is optimized for low-power consumption. It has two software selectable modes for power reduction: Idle and Power-down. In addition, the clock to all unused peripheral blocks can be switched off. The instruction set is based on that of the 80C51. The P83CL882 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. Port 2 is not incorporated, therefore there is no external data or memory access and the MOVX operations cannot be used. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME P83CL882T/xxx TSSOP32 DESCRIPTION plastic thin shrink small outline package; 32 leads; body width 6.1 mm VERSION SOT487-1 2001 Jun 19 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2001 Jun 19 (2) (2) 4 Philips Semiconductors 80C51 Ultra Low Power (ULP) telephony controller BLOCK DIAGRAM (2) T0 T1 MOUT2 to MOUT0 MIN RST XTAL1 XTAL2 VDD VSS VDDP VSSP TIMER 0 TIMER 1 CPU 80C51 ROM MSK MODEM MODE AND TEST CONTROL fosc AMPLITUDE CONTROLLED OSCILLATOR OSCILLATOR fosc COMPARATOR BLOCK XTM SELECT fpsc PSC1 PSC2 fper fper RAM IRST internal bus mode selection INTERRUPT CONTROL P83CL882 fpsc fper fpsc handbook, full pagewidth 4 PORT CONTROL PORT 0 PORT 1 PORT 3 TIMER 2 I2C-BUS INTERFACE WATCHDOG TIMER MGU258 P0 P1 P3 T2 T2EX T2OUT SCL (1) (1) (1) (1) SDA (1) Product specification P83CL882 (1) Alternative function of Port 1. (2) Alternative function of Port 3. Fig.1 Simplified block diagram. Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 5 5.1 PINNING INFORMATION Pin configuration P83CL882 handbook, halfpage P3.3 P3.4/T0 P3.5/T1 P3.6 P3.7 P1.2/INT4/T2 P1.1/INT3/T2EX P1.0/INT2 VSS 1 2 3 4 5 6 7 8 32 VSSP 31 VDDP 30 P1.5/INT7 29 P1.4/INT6/CLKOUT 28 P1.3/INT5 27 P0.7 26 P0.6 25 P0.5 P83CL882 9 24 P0.4 23 P0.3 22 P0.2 21 P0.1 20 P0.0 19 P1.7/INT9/SDA 18 P1.6/INT8/SCL 17 MIN MGU265 VDD 10 XTAL2 11 XTAL1 12 RST 13 P3.0/MOUT0 14 P3.1/INT1/MOUT1 15 P3.2/INT0/MOUT2 16 Fig.2 Pin configuration (TSSOP32/SOT487-1). 2001 Jun 19 5 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 5.2 Pin description Pin description for TSSOP32 (SOT487-1) SYMBOL P3.3 P3.4/T0 P3.5/T1 P3.6 P3.7 P1.2/INT4/T2 P1.1/INT3/T2EX P1.0/INT2 VSS(1) VDD(1) XTAL2 XTAL1 RST P3.0/MOUT0 P3.1/MOUT1/INT1 P3.2/MOUT2/INT0 MIN P1.6/INT8/SCL P1.7/INT9/SDA P0.0 to P0.7 P1.3/INT5 P1.4/INT6/CLKOUT P1.5/INT7/T2OUT VDDP(1) VSSP Note 1. For high current drive capability on I/Os all supply pins should be connected. (1) P83CL882 Table 1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 to 27 28 29 30 31 32 TYPE I/O I/O I/O I/O I/O I/O I/O I/O S S O I I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O S S DESCRIPTION Port 3: P3.3 to P3.7; bidirectional I/O port with two alternative functions. P3.4 also serves as the Timer 0 external count input (T0). P3.5 also serves as the Timer 1 external count input (T1). Port 1: P1.2 to P1.0; bidirectional I/O port with alternative functions. INT4, INT3 and INT2 are the external interrupts 4, 3 and 2 respectively. P1.2 also serves as Timer 2 input (T2). P1.1 also serves as Timer 2 external input (T2EX). ground power supply voltage crystal output crystal input; external clock input reset input/output pin; active LOW Port 3: P3.0 to P3.2; bidirectional I/O port with alternative functions. MOUT2 to MOUT0 are the MSK outputs (mapped on the lower 3 bits of Port 3). P3.2 also serves as the external interrupt 0 input (INT1) and P3.1 as the external interrupt 1 input (INT0). MSK input Port 1: P1.6 and P1.7; can only be used as open-drain output or high-impedance input. Alternative functions: INT8 and INT9, external interrupt 8 and 9. SCL and SDA I2C-bus interface clock and data. Port 0: 8-bit bidirectional I/O port. Every port pin can be used as open-drain, standard port, high-impedance input or push-pull output. Port 1: P1.3 to P1.5; bidirectional I/O port with alternative functions INT5, INT6 and INT7: external interrupt 5 to 7. P1.4 also serves as auxiliary clock output (CLKOUT). P1.5 also serves as the Timer 2 output (T2OUT). periphery (I/O) positive supply voltage periphery (I/O) ground 2001 Jun 19 6 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6 6.1 FUNCTIONAL DESCRIPTION Oscillator circuitry Table 2 P83CL882 Comparator select bits in SYSCON SFR XTM 0 1 0 1 DESCRIPTION oscillator enabled; analog comparator enabled don't use oscillator enabled; hysteresis comparator enabled oscillator stopped; hysteresis comparator enabled SELECT 0 0 1 1 The on-chip Amplitude Controlled Oscillator (ACO) circuitry is a single-stage inverting amplifier biased by an internal feedback resistor Rfb. The oscillator circuit is shown in Fig.3. Two comparators with different characteristics can be used with the on-chip crystal oscillator. The first one is an analog comparator built around a differential amplifier and is intended to be selected when an external ceramic or crystal resonator is connected to the chip. The other comparator has a Schmitt trigger input with a bigger hysteresis which is especially useful when the P83CL882 is driven from an external clock source. Two bits in the SYSCON SFR: SELECT and XTM, are used to configure the oscillator. The SELECT bit (SYSCON.1) enables the analog comparator or the hysteresis comparator. With XTM (SYSCON.0) = 1 (or in Power-down mode; PCON.1 = 1) the oscillator is switched off and the current consumption of the oscillator is reduced to zero. 6.1.1 CLOCK OSCILLATOR CONNECTIONS No external components are needed when a quartz crystal is used to drive the oscillator. When an external ceramic resonator is used to drive the oscillator, external components may be required depending upon the ceramic resonator type; refer to the product specification. Two different resonator configurations are shown in Figs 4a and 4b. To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 floating, as shown in Fig.4c. If the amplitude of the input signal is less than VDD to VSS or if a sine wave is applied, capacitive decoupling is needed as shown in Fig.4d. ANACOMP enable fosc PSC1 enable Rfb MGT281 fpsc HYSTCOMP PSC2 fper SELECT XTAL1 XTAL2 XTM enable Fig.3 Oscillator. 2001 Jun 19 7 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 handbook, full pagewidth STANDARD QUARTZ OSCILLATOR XTAL1 XTAL2 OSCILLATOR WITH EXTERNAL CAPACITORS (QUARTZ or PXE) XTAL1 XTAL2 (a) (b) EXTERNAL CLOCK (SQUARE) XTAL1 XTAL2 n.c. EXTERNAL CLOCK (SINE) XTAL1 XTAL2 n.c. (c) (d) MBH986 Fig.4 Alternative oscillator configurations. 2001 Jun 19 8 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.1.2 RESONATOR REQUIREMENTS FOR THE ACO P83CL882 In Fig.5a the complete Pierce type oscillator is shown, while Fig.5b presents the corresponding equivalent circuit used for calculations. handbook, halfpage XTAL1 XTAL2 At the resonance frequency the behaviour of a crystal resonator can be approximated by its equivalent circuit, as shown in Fig.5b. The values of the components Rs, L, Cs and Co in the crystal equivalent circuit are usually specified in the data sheet of the crystal supplier. The inverting amplifier is replaced by its equivalent circuit, the current source with the transconductance gm and the output impedance Rg; as shown in Fig.5b. With some calculation the condition below can be found, which estimates a minimal value for gm of the inverter which is required for the oscillation: 2 2 1 4 g m 4 x R s x o x C p + ----- + -----Rf Rg handbook, halfpage -gm C1 C2 MBL311 a. Crystal oscillator. Rs L Co Cs XTAL2 XTAL1 Where Ce C p = C o + C f + -----2 and C1 = C2 = Ce Rf is an internal bias resistor, and Cf stands for all of the parasitic capacitors parallel to the gate, from input to the output. Parasitic capacitors from input or output to ground are included with C1 or C2. The input impedance of a CMOS gate is high and can be neglected. It is advised to keep the wiring between chip and resonator as short as possible. Rf VI C1 Cf Ig = -gm x VI Rg C2 MBL310 b. Crystal oscillator equivalent circuit. Fig.5 Crystal oscillator and its equivalent circuit. 2001 Jun 19 9 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.1.3 ON-CHIP CLOCKS P83CL882 The microcontroller does not need a clock signal to run instructions, because the CPU is built using the Philips exclusive handshake technology. The peripheral blocks however are connected to a clock for synchronization with the outside world (e.g. MSK) or for a timed application (e.g. Timer 2). The block related SFRs (peripheral function) are therefore updated/modified with the applied clock. Two prescalers (PSC1 and PSC2) are implemented which allow the generation of two programmable clock signals fpsc and fper for internal usage. Signal fpsc from PSC1 is the default input clock of the timer blocks. The complete timer functionality is specified in the Section 6.5. Connected timers are the three 16-bit timers Timer 0, 1 and 2 and the 8-bit Watchdog Timer. The time interval of the connected timers can be adjusted by programming of PSC1. The output frequency fpsc can be changed by selecting the division factor with the bits PRESC.[2:0], (see Table 7). All peripheral blocks, which require a clock signal: MSK, and I2C-bus interface are connected to the clock signal fper. PSC2 can be programmed by setting bits PRESC.4 and PRESC.3 (see Table 7). The choice of the division factor must guarantee that all of the peripheral blocks are within their specification, specially if an external clock source of up to 12 MHz is applied. Additionally Timer 1 and Timer 0 have a multiplexer on the clock input to choose from 4 different clock sources. The multiplexers are switched by setting user controllable bits in the SYSCON SFR (bits 7 to 4). In the default setting both timers are incrementing on the clock signal fpsc coming from PSC1. Timer 1 and Timer 0 can however also run on clock signal fper coming from PSC2. If used in the proper way this flexibility on the timer input sources can substantially contribute to a decrease in power consumption. Ideas and tips to reduce power consumption are given in Chapter 9. The clock source of Timer 1 and Timer 0 can also be switched to an external clock input signal T1 or T0 which are multiplexed with one of the device input pins. This mode is also functional even when there is no system clock available. This means when a clock source is supplied on a port pin Timer 1 or Timer 0 can count and generate interrupts even when the chip is in Power-down mode. More details are specified in Section 6.5. The last multiplexer input to Timer 1 and Timer 0 is an auxiliary mode which can be used to obtain the operation speed from the handshake CPU. If this mode is activated for the Timer 1 input source, the timer increments on every ROM request. This means the timer increments by three for a three byte instruction and by two for a two byte instruction etc. If the auxiliary mode is activated for Timer 0 the timer increments on every instruction executed by the CPU. This means the timer register holds the number of instructions executed in a certain time frame. More ideas and tips on how these clock source modes can be used together with the handshake CPU can be found in Chapter 9. Table 3 Timer 1 input source select modes Bits T1SRC[1:0] are defined in SYSCON SFR. T1SRC1 0 0 1 1 T1SRC0 0 1 0 1 DESCRIPTION fpsc is the Timer 1 clock input T1 is the Timer 1 clock input the ROMreq signal is the Timer 1 clock input fper is the Timer 1 clock input Table 4 Timer 0 input source select modes Bits T0SRC[1:0] are defined in SYSCON SFR. T0SRC1 0 0 1 1 T0SRC0 0 1 0 1 DESCRIPTION fpsc is the Timer 0 clock input T0 is the Timer 0 clock input the InstrReq signal is the Timer 0 clock input fper is the Timer 0 clock input 2001 Jun 19 10 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 handbook, full pagewidth f psc WATCHDOG TIMER TIMER 2 T1 ROMReq T1SRC1/T1SRC0 T0SRC1/T0SRC0 power-down f psc OSCILLATOR AND COMPARATOR f osc f per T0 InstrReq TIMER 1 TIMER 0 XTAL1 XTAL2 MSK MODEM I2C-BUS SELECT XTM f osc SYNC CPU synchronisation PORTS AUXSW EXTCK AUXCLK to pin P1.4 CLKOUT MGU266 Fig.6 Clock overview. 2001 Jun 19 11 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.1.3.1 Prescaler Register (PRESC) P83CL882 Reset value of PRESC SFR is XXX0 0000 (division factor 1 for PSC1 and PSC2). Table 5 7 EXTCK Table 6 BIT 7 6 5 4 to 0 Table 7 Prescaler Register (SFR address F3H) 6 AUXSW 5 SYNC 4 PRESC.4 3 PRESC.3 2 PRESC.2 1 PRESC.1 0 PRESC.0 Description of PRESC bits SYMBOL EXTCK AUXSW SYNC DESCRIPTION Switches AUXCLK to device pin P1.4 (CLKOUT). Auxiliary Clock Switch. If AUXSW = 0; then AUXCLK equals fpsc. If AUXSW = 1; then AUXCLK equals fper. Switches the CPU to Synchronous mode. PRESC.[4:0] These bits define the division factors for PSC1 and PSC2; see Table 7. Division factors for PSC1 and PSC2 DIVISION FACTOR PSC2 (fosc/fper) 1 2 4 8 - - - - - - - - 6.1.4 PSC1 (fosc/fpsc) - - - - 1 2 4 6 8 10 12 16 PRESC.4 0 0 1 1 X X X X X X X X PRESC.3 0 1 0 1 X X X X X X X X PRESC.2 X X X X 0 0 0 0 1 1 1 1 PRESC.1 X X X X 0 0 1 1 0 0 1 1 PRESC.0 X X X X 0 1 0 1 0 1 0 1 AUXILIARY CLOCK SIGNAL MODES The 3 most significant bits in the Prescaler Register (see Tables 5 and 6) are used to enable additional clocking options. A multiplexer is implemented (see Fig.6) to choose between fpsc and fper as the source for AUXCLK. The multiplexer is operated by bit AUXSW (PRESC.6). With bit EXTCK (PRESC.7) the AUXCLK is fed to pin P1.4 (CLKOUT) for external use (initialize the port accordingly). Setting bit SYNC (PRESC.5) connects the AUXCLK to the instruction request input of the CPU. In this way the CPU is synchronised to the clock and an instruction is executed at every clock pulse of AUXCLK. In order to obtain exactly one instruction per clock cycle the period for AUXCLK must always be longer than the length of the slowest instruction. 2001 Jun 19 12 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.1.5 Table 8 7 T1SRC1 Table 9 BIT 7 6 5 4 3 2 1 0 SELECT XTM comparator select bit; see Table 2 oscillator disable bit; see Table 2 SYSTEM CONTROL REGISTER (SYSCON) System Control Register (SFR address B4H) 6 T1SRC0 5 T0SRC1 4 T0SRC0 3 - 2 - 1 P83CL882 0 XTM SELECT Description of SYSCON bits SYMBOL T1SRC1 T1SRC0 T0SRC1 T0SRC0 - do not use These 2 bits select the clock source for Timer 0; see Table 4. DESCRIPTION These 2 bits select the clock source for Timer 1; see Table 3. 2001 Jun 19 13 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2 6.2.1 The CPU GENERAL P83CL882 Ultra Low Power (ULP), points to the special 80C51 CPU architecture used in this device allowing significant power saving. The CPU of the P83CL882 is realized in the Philips exclusive asynchronous handshaking technology, which is completely different to usual implementations of this core. The processor does not need a clock signal to run instructions. Every function within the CPU is self timed and always runs at the maximum speed that the silicon die under the current operating conditions allows (supply voltage and temperature). The advantage is the combination of a high computing power with reduced average power consumption and low EMC noise generation. Details about speed and energy consumption per instruction can be found in Chapter 8. Summary of the CPU features: * No CPU clock is needed * Only useful bytes are fetched from the program memory; the dummy read cycles which exist in the standard 80C51 have been eliminated to save power * To further speed up the program execution; there is always a pre-fetch of the next byte of code from memory during the execution of the current instruction; in the case of a jump the pre-fetched byte is discarded * In Idle mode the CPU power is reduced to leakage; only the enabled peripheral blocks consume power but can be switched off independently * The only need for a clock is as a timing reference for timers/counters and to generate the timing for the I/O lines to synchronise with the off-chip world. 6.2.2 RESET OPERATION There are two possibilities to reset the CPU (see Fig.7): * Watchdog Timer reset * External reset via I/O pin RST. If an internal reset is executed (Watchdog Timer), the reset pin RST will be pulled to ground which can be used as reset signal for other ICs. The reset pin is LOW for at least 1024 clock cycles, and released 16 clock cycles prior to first code fetch (see Figs 8 and 9). handbook, full pagewidth VDD Rpu RST (external reset) LOGIC VSS WATCHDOG TIMER internal reset MGU267 Fig.7 Reset sources. 2001 Jun 19 14 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2.2.1 Watchdog Timer reset P83CL882 If the Watchdog Timer expires, it will trigger a reset. Watchdog Timer 1024 clocks CPU activity 16 clocks CPU start RST output MGT287 Fig.8 Watchdog Timer reset timing. 2001 Jun 19 15 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2.2.2 External reset via RST P83CL882 An external device can cause a chip reset, if the reset pin RST is pulled to ground. minimum 8 clocks External applied RST RST by counter 8 clocks maximum 16384 = 214 clocks 16 clocks CPU activity MGT286 a. Short external reset. External applied RST RST by counter 8 clocks maximum 16384 = 214 clocks 16 clocks CPU activity MGT546 b. Long external reset. Fig.9 External reset. 2001 Jun 19 16 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2.3 IDLE AND POWER-DOWN OPERATION P83CL882 Idle and Power-down are power saving modes of the microcontroller that can be activated when no CPU activity is required. These two modes are extremely useful for the asynchronous CPU, because they offer the possibility to profit from the speed of the CPU and to save power as soon as the task is finished. Idle mode stops the code execution of the CPU, but the internal oscillator remains active, and also all peripheral functions connected to the on-chip clock signal. Unused blocks can be switched off independently. However, during Power-down mode the clock oscillator is stopped and therefore also all peripheral blocks will stop their activity. * The second way of terminating the Idle mode is with an internal or external hardware reset. Reset redefines all SFRs but does not affect the on-chip RAM. The source of an internal reset is the Watchdog Timer if the preset delay has expired. 6.2.3.2 Power-down mode The instruction that sets PCON.1 (PCON SFR) is the last instruction executed in the normal operating mode before the Power-down mode is activated. During Power-down mode, the RAM and all of the registers maintain their data: the CPU status, the stack pointer, program counter, program status word and accumulator. There are two ways to terminate the Power-down mode: * Activation of any of the interrupts listed below will cause PCON.1 to be cleared by hardware thus terminating the Power-down mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Power-down mode. Interrupts which can generate a wake-up from power-down: - External interrupts (INT0 to INT9) - Timer 0 and Timer 1: only when pins T0 and T1 are used as the external timer source input (SYSCON SFR bits 7 to 4) * The second way of terminating the Power-down mode is with an internal or external hardware reset. Reset does not affect the on-chip RAM, but all SFRs are set to the default value. 6.2.3.1 Idle mode The following functions remain active during Idle mode: * Timers 0, 1 and 2 * Wake-up counter * Watchdog Timer counter * MSK modem * I2C-bus interface * External interrupt. The instruction that sets PCON.0 (PCON SFR) is the last instruction executed in the normal operating mode before the Idle mode is activated. The RAM and all of the registers are preserved and maintain their data during Idle mode: the CPU status, the stack pointer, program counter, program status word and accumulator. There are two ways to terminate the Idle mode: * Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. 2001 Jun 19 17 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2.3.3 Power Control Register (PCON) P83CL882 The reduced power modes are activated by software using this special function register. PCON is not bit addressable. The reset value of PCON = 0000 0000. Table 10 Power Control Register (SFR address 87H) Bits PCON[7:2] are reserved and must be kept to logic 0. 7 0 6 0 5 0 4 0 3 0 2 0 1 PD 0 IDL Table 11 Reduced power modes selection PD 0 0 1 1 6.2.4 IDL 0 1 0 1 CPU running activates the Idle mode activates the Power-down mode DESCRIPTION CPU START-UP TIMING 6.2.4.1 CPU start-up after reset Three possibilities on how the CPU can start executing code after a reset phase are described below. When the CPU is triggered to wake-up after a power-on reset (see Fig.8), the clock oscillator usually needs some time to ramp up. To allow the oscillator to stabilize the CPU contains a down counter for a fixed delay of 1024 + 16 clock cycles. After this delay the CPU starts with code execution. When CPU start-up is initiated from an external reset (see Fig.9), the down counter is not initialized and the time between reset going active and first code execution can be maximum 16400 clock cycles. When a CPU start-up is after a Watchdog Timer reset (see Fig.8), the RST pin will be pulled low for 1024 clock cycles. Another 16 clocks later the CPU will start executing code. 6.2.4.2 CPU start-up after power-down After wake-up from Power-down mode (see Fig.10) the user has the possibility to shorten the start-up time by programming the Wake-up Counter Register (WKCON). This can be useful when an external clock source is used instead of the on-chip oscillator, or when the accuracy of the time reference is not needed immediately after a restart. This feature enables power saving and fast wake-up in applications where the CPU frequently goes into Power-down mode. The wake-up delay can be calculated as shown in Table 13. 2001 Jun 19 18 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.2.5 WAKE-UP COUNTER REGISTER (WKCON) P83CL882 Table 12 Wake-up Counter Register (SFR address DDH) 7 WKCON.7 6 WKCON.6 5 WKCON.5 4 WKCON.4 3 WKCON.3 2 WKCON.2 1 WKCON.1 0 WKCON.0 Table 13 Description of WKCON bits BIT 7 to 0 SYMBOL WKCON.[7:0] DESCRIPTION The wake-up delay can be calculated as follows: Wake-up delay = (1024 - 4) x WKCON. Where WKCON is the content of the Wake-up Counter Register. WKCON = 00H: (default) wake-up delay = 1024 clocks WKCON = CCH: wake-up delay = 208 clocks WKCON = FFH: wake-up delay = 4 clocks. wake-up event oscillator stop start unstable clock CLOCK programmable delay CPU activity CPU stop CPU start MGT288 Fig.10 Wake-up timing from power-down. 2001 Jun 19 19 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3 Interrupt controller P83CL882 In order to service interrupt requests coming from external events and from the on-chip peripherals the P83CL882 offers a 17 source, two priority level nested interrupt system. A detailed description of the interrupt process is given in the following sections. Table 14 shows the available interrupts with each vector address and Table 15 shows an overview of all the interrupt related SFRs. The detailed interrupt related SFR description can be found in Sections 6.3.4 to 6.3.10. 6.3.1 GENERAL In the event of several interrupts with the same priority level, the order of sequence in which they will be serviced is determined by the scanning order. The interrupt highest in the scanning list will always be served first, interrupts lower in the scanning list will be served in the order as shown in Fig.12. No interrupt will be lost. Table 14 Available interrupts (ordered by vector address) HW = hardware; SW = software. SOURCE INT 0 Timer 0 INT 1 Timer 1 I2C-bus Timer 2 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 MSK modem transmitter MSK mode receiver Watchdog Timer SYMBOL X0 T0 X1 T1 S1 T2 X2 X3 X4 X5 X6 X7 X8 X9 MTI MRI WDI VECTOR CLEARED (HEX) BY 0003 000B 0013 001B 002B 0033 003B 0043 004B 0053 005B 0063 006B 0073 0083 008B 00B3 HW HW HW HW SW SW SW SW SW SW SW SW SW SW SW SW SW Each interrupt vector points to a separate location in program memory for its service routine. Each source can be individually enabled or disabled by its corresponding bit in the Interrupt Enable Registers (IEN0, IEN1 and IEN2). The priority level is selected via the Interrupt Priority Registers (IP0, IP1 and IP2). All available interrupts can be globally disabled or enabled. The interrupt controller samples all active sources during one instruction cycle. Evaluation of the interrupts is then performed. A priority decoder decides which interrupt is serviced. Each interrupt has its own vector pointing to an 8 bytes long memory segment. A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt i.e. only two interrupt levels are possible. Between the RETI instruction (Return from Interrupt) and the execution of a next interrupt at least one instruction of the lower program level is executed. The interrupt service with different priorities is shown in Fig.11. An interrupt is performed with a long subroutine call (LCALL) to a vector address, which is determined by the respective interrupt. During LCALL the Program Counter (PC) is pushed onto the stack. Returning from interrupt with RETI, the PC is popped from the stack. 2001 Jun 19 20 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Table 15 Interrupt related SFRs SFR IEN0 IEN1 IEN2 IP0 IP1 IP2 IX1 ISE1 IRQ1 DESCRIPTION interrupt enable register 0 interrupt enable register 1 (INT2 to INT9) interrupt enable register 2 interrupt priority register 0 interrupt priority register 1 (INT2 to INT9) interrupt priority register 2 external interrupt polarity register 1 external interrupt sensitivity register 1 external interrupt request flag register 1 SFR ADDRESS A8H E8H F1H B8H F8H F9H E9H E1H C0H P83CL882 RESET VALUE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 handbook, full pagewidth Level 21 RETI Level 20 RETI Interrupt level 2x RETI Interrupt level 1 IP = 1 IP = 0 IP = 1 Program level 0 one instruction MGR125 Fig.11 Interrupt hierarchy. 2001 Jun 19 21 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 INTERRUPT SOURCES X0 IEN0 IEN1 IEN2 IP0 IP1 IP2 HIGH LOW S1 X5 MRI T0 T2 X6 MTI X1 X2 X7 decreasing priority within same level T1 X3 X8 X4 X9 WDI MGU259 Fig.12 Interrupt assignment and priorities (listed by scanning order). 2001 Jun 19 22 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.2 INTERRUPT PROCESS P83CL882 1. Sample the interrupt lines. The interrupt lines are latched at the beginning of each instruction cycle. 2. Analyse the requests. The sampled interrupt lines will be analysed with respect to the relevant Interrupt Enable Register (IENx) and Interrupt Priority Register (IPx). The process will deliver the vector of the highest interrupt request and the priority information. Depending on the interrupt level and the priority of the interrupt in progress, an interrupt request to the core is performed. The vector address will be passed to the core process. 3. Interrupt request to core. a) Level 0: the interrupt request to the core is performed, when at least one instruction is performed since the RETI from Level 1. b) Level 1: the interrupt request is performed, when at least one instruction is performed since the RETI from Level 21 and the request has high priority. c) Level 20: no request is performed. d) Level 21: no request is performed. 4. Update the interrupt level. a) Level 0: in the event of a high priority interrupt the new level will be Level 20; if it is a low priority interrupt, the new level will be Level 1. b) Level 1: in the event of a high priority interrupt, the new level will be Level 21; a low priority interrupt is not performed, the level is unchanged; on RETI the new level will be Level 0. c) Level 20: on RETI; the new level is Level 0. d) Level 21: on RETI; the new level is Level 1. e) Level 1: on RETI; the new level is Level 0. f) Level 0: the new level is Level 0. 5. Clearing the flags. During the forced LCALL the interrupt flag of the relevant interrupt is cleared by hardware, if applicable, otherwise by software. 6. Idle and Power-down. When Idle (PCON.0) or Power-down (PCON.1) is set, the interrupt controller waits for the wake-up signal. Because the interrupt controller is waiting for wake-up, all activity in the circuit will be stopped, thus no handshake can be completed. The wake-up signal for Idle is the OR of all the interrupt request bits and the reset. For Power-down the wake-up signal is built only with the Port 1 external interrupt request flags (X2 to X9) and the reset (external reset). 6.3.3 PORT 1 INTERRUPTS Eight Port 1 lines can be used as external interrupt inputs (X2 to X9). When enabled by IEN1 SFR, each of these interrupts may wake-up the device from Idle or Power-down. These external interrupts can each independently be programmed to positive and negative polarity and to edge and level sensitivity by setting SFR IX1 and ISE1 (see Table 34). Figure 12 shows programming of polarity and sensitivity of the Port 1 interrupts. When a valid event occurs on an enabled Port 1 interrupt, the corresponding bit in the Interrupt Request Flags Register will be set (IRQ1). The interrupt request flags must be cleared by software. 2001 Jun 19 23 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.4 INTERRUPT ENABLE REGISTER 0 (IEN0) P83CL882 Table 16 Interrupt Enable Register 0 (SFR address A8H) 7 EA 6 ET2 5 ES1 4 - 3 ET1 2 EX1 1 ET0 0 EX0 Table 17 Description of IEN0 bits Logic 0 = interrupt disabled; logic 1 = interrupt enabled. BIT 7 6 5 4 3 2 1 0 6.3.5 SYMBOL EA ET2 ES1 - ET1 EX1 ET0 EX0 DESCRIPTION General enable/disable control. If EA = 0, no interrupt is enabled; if EA = 1, any individually enabled interrupt will be accepted. enable T2 interrupt enable I2C-bus interrupt reserved enable Timer 1 interrupt (T1) enable external interrupt 1 enable Timer 0 interrupt (T0) enable external interrupt 0 INTERRUPT ENABLE REGISTER 1 (IEN1) Table 18 Interrupt Enable Register 1 (SFR address E8H) 7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2 Table 19 Description of IEN1 bits Logic 0 = interrupt disabled; logic 1 = interrupt enabled. BIT 7 6 5 4 3 2 1 0 SYMBOL EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 enable external interrupt 9 enable external interrupt 8 enable external interrupt 7 enable external interrupt 6 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 DESCRIPTION 2001 Jun 19 24 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.6 INTERRUPT ENABLE REGISTER 2 (IEN2) P83CL882 Table 20 Interrupt Enable Register 2 (SFR address F1H) 7 EWDI 6 - 5 - 4 - 3 - 2 - 1 EMTI 0 EMRI Table 21 Description of IEN2 bits Logic 0 = interrupt disabled; logic 1 = interrupt enabled. BIT 7 6 5 4 3 2 1 0 6.3.7 SYMBOL EWDI - - - - - EMTI EMRI enable Watchdog Timer interrupt reserved reserved reserved reserved reserved enable MSK transmitter interrupt enable MSK receiver interrupts DESCRIPTION INTERRUPT PRIORITY REGISTER 0 (IP0) Table 22 Interrupt Priority Register 0 (SFR address B8H) 7 - 6 PT2 5 PS1 4 - 3 PT1 2 PX1 1 PT0 0 PX0 Table 23 Description of IP0 bits Logic 0 = low priority; logic 1 = high priority. BIT 7 6 5 4 3 2 1 0 SYMBOL - PT2 PS1 - PT1 PX1 PT0 PX0 reserved Timer 2 interrupt priority level I2C-bus interrupt priority level reserved Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION 2001 Jun 19 25 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.8 INTERRUPT PRIORITY REGISTER 1 (IP1) P83CL882 Table 24 Interrupt Priority Register 1 (SFR address F8H) 7 PX9 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2 Table 25 Description of IP1 bits Logic 0 = low priority; logic 1 = high priority. BIT 7 6 5 4 3 2 1 0 6.3.9 SYMBOL PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 external interrupt 9 priority level external interrupt 8 priority level external interrupt 7 priority level external interrupt 6 priority level external interrupt 5 priority level external interrupt 4 priority level external interrupt 3 priority level external interrupt 2 priority level DESCRIPTION INTERRUPT PRIORITY REGISTER 2 (IP2) Table 26 Interrupt Priority Register 2 (SFR address F9H) 7 PWDI 6 - 5 - 4 - 3 - 2 - 1 PMTI 0 PMRI Table 27 Description of IP2 bits Logic 0 = low priority; logic 1 = high priority. BIT 7 6 5 4 3 2 1 0 SYMBOL PWDI - - - - - PMTI PMRI reserved reserved reserved reserved reserved MSK transmitter interrupt priority level MSK receiver interrupt priority level DESCRIPTION Watchdog Timer interrupt priority level 2001 Jun 19 26 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.10 INTERRUPT REQUEST FLAG REGISTER 1 (IRQ1) P83CL882 Table 28 Interrupt Request Flag Register 1 (SFR address C0H) 7 IQ9 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2 Table 29 Description of IRQ1 bits BIT 7 6 5 4 3 2 1 0 6.3.11 SYMBOL IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 external interrupt 9 request flag external interrupt 8 request flag external interrupt 7 request flag external interrupt 6 request flag external interrupt 5 request flag external interrupt 4 request flag external interrupt 3 request flag external interrupt 2 request flag DESCRIPTION INTERRUPT POLARITY AND SENSITIVITY REGISTERS 6.3.11.1 Interrupt Polarity Register 1 (IX1) Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity of the corresponding external interrupt. If the interrupt sensitivity bit (ISE1 register, Section 6.3.11.2) is set to `level' sensitive then a logic 1 corresponds to active HIGH level and logic 0 to active LOW level. If the ISE1 register is set to `edge' sensitive then a logic 1 corresponds to a rising edge and a logic 0 to a falling edge. See also Table 34 and Fig.12. Table 30 Interrupt Polarity Register 1 (SFR address E9H) 7 IX9 6 IX8 5 IX7 4 IX6 3 IX5 2 IX4 1 IX3 0 IX2 Table 31 Description of IX1 bits BIT 7 to 0 SYMBOL IX9 to IX2 DESCRIPTION external interrupt 9 to 2 polarity level 2001 Jun 19 27 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.3.11.2 Interrupt Sensitivity Register 1 (ISE1) P83CL882 Writing either a logic 1 or logic 0 to an Interrupt Sensitivity Register bit sets the type of the corresponding external interrupt to edge sensitive (logic 1) or level sensitive (logic 0). Table 32 Interrupt Sensitivity Register 1 (SFR address E1H) 7 ISE9 6 ISE8 5 ISE7 4 ISE6 3 ISE5 2 ISE4 1 ISE3 0 ISE2 Table 33 Description of ISE1 bits BIT 7 to 0 SYMBOL ISE9 to ISE2 external interrupt 9 to 2 sensitivity DESCRIPTION 6.3.11.3 Interrupt polarity and sensitivity options Table 34 Interrupt polarity and sensitivity options `n' denotes the bit position in the SFRs IX1 and ISE1. IX1.n 0 1 0 1 ISE1.n 0 0 1 1 LOW-level sensitive HIGH-level sensitive falling edge sensitive rising edge sensitive DESCRIPTION positive level ISE1.n PORT1 P1.n IX1.n negative level IEN1.n IRQ1.n positive edge negative edge MGT290 Fig.13 Polarity and sensitivity of Port 1 interrupts. 2001 Jun 19 28 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.4 Port control logic 6.4.2 PORT I/O CONFIGURATION P83CL882 Four 8-bit I/O ports are implemented in the device. Some of these general purpose I/Os are multiplexed with alternative functions. Port 0 is the only port with no multiplexed alternative functions. Port 3 and a part of Port 1 are multiplexed with analog functions. Every port bit can be independently configured in 4 different modes. 6.4.1 PORT FUNCTIONALITY Port 0 8-bit bidirectional I/O port with no alternative functions. Every port pin can be used as open-drain, standard port, high-impedance input or push-pull output. Port 0 is used during emulation mode. Port 1 8-bit bidirectional I/O port with alternative functions. Every port, except P1.6 and P1.7 can be used as open-drain, standard port, high-impedance input or push-pull output. * P1.0 to P1.7 provides the inputs for the external interrupts INT2 to INT9; the interrupts are enabled by selecting the proper bit in the interrupts enable register * P1.1 and P1.2 provide the Timer 2 external trigger input (T2EX) and the Timer 2 external count input (T2) * P1.4 provides the clock output CLKOUT (fpsc or fper) * P1.5 provide the Timer 2 clock output of the clock-output mode (T2OUT); to enable output the data SFR must contain logic 1s * P1.6 and P1.7 provide the I2C-bus clock and data I/O, SCL and SDA. P1.6 and P1.7 can only be configured as open-drain output or high-impedance input; there is no clamp diode to VDD. I2C-bus signals are connected to the port if bit ENS1 (S1CON SFR) is set to logic 1. Port 2 Not used. Port 3 8-bit bidirectional I/O port with alternative functions. Every port can be used as open-drain, standard port, high-impedance input or push-pull output. * P3.0 to P3.2 provide the MSK output signals MOUT0, MOUT1 and MOUT2 * P3.4 also provides the Timer 0 external clock input * P3.5 also provides the Timer 1 external clock input. Each port bit consists of a data latch, two configuration latches, an output driver and an input buffer. The I/O port configurations are determined by the settings in the port configuration SFRs, PnCFGA and PnCFGB, where `n' indicates the specific port number (0, 1, 3 and 4). The combination of 2 bits in each of the 2 configuration SFRs relates to the output setting for the corresponding port pin, allowing any combination of the 4 I/O modes to be mixed on those port pins. The port I/O configuration types are shown in Fig.14 and described in Sections 6.4.2.1 to 6.4.2.4. 6.4.2.1 Open-drain Quasi-bidirectional I/O with n-channel open-drain output. Use as an output requires the connection of an external pull-up resistor; all pins have ESD protection diodes against VDD and VSS, except for the I2C-bus pins P1.6 and P1.7, which have no ESD protection to VDD. 6.4.2.2 Standard port Quasi-bidirectional I/O with pull-up; the strong pull-up `p1' is turned on for three clock (fosc) edges after a LOW-to-HIGH transition in the port latch; after these three clock edges the port is only weakly driven through `p2' and `very weakly' driven through `p3' (see Fig.14b). 6.4.2.3 High-impedance input This mode turns off all output drivers on a port. The pin will not source or sink current and may be used as an input-only pin. (see Fig.14c). In order not to increase the current consumption the high-impedance input should not float. 6.4.2.4 Push-pull Output with drive capability in both polarities; under this mode, pins can only be used as outputs (see Fig.14d). 2001 Jun 19 29 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Table 35 Port I/O configuration types `n' indicates the specific port number (0, 1, 3 and 4). TYPE Open-drain Standard port High-impedance input Push-pull PnCFGA 0 1 0 1 PnCFGB 0 0 1 1 NORMAL PORTS open-drain quasi-bidirectional high-impedance input push-pull P83CL882 I2C-BUS PORTS open-drain open-drain high-impedance input open-drain Table 36 Reset state of port related SFRs SFR P0 P0CFGA P0CFGB P1 P1CFGA P1CFGB P3 P3CFGA P3CFGB Note 1. This means all ports, except P0.2, P0.3, P0.4, P1.6 and P1.7 are initialized in standard port configuration driving a weak logic 1. Port 0.2 and P0.3 are initialised as open-drain outputs, floating. P0.4 is initialised as bidirectional, driving a strong logic 0. I2C-bus I/Os P1.6 and P1.7 are initialised in open-drain configuration, floating. The configuration registers (P1CFGA.7 to 6 and P1CGB.7 to 6) are however configured as standard port configuration but the connections to the port PMOS transistors are not present. DESCRIPTION Port 0 output data Port 0 Configuration A Port 0 Configuration B Port 1 output data Port 1 Configuration A Port 1 Configuration B Port 3 output data Port 3 Configuration A Port 3 Configuration B SFR ADDRESS (HEX) 80 8E 8F 90 9E 9F B0 BE BF STATE AFTER RESET(1) 1110 1111 1111 0011 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 2001 Jun 19 30 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 handbook, full pagewidth VDD this diode is not implemented on the I2C-bus pins I/O pin Q from port latch VDD external external pull-up n VSS VSS MBK004 input data a. Open-drain. handbook, full pagewidth strong pull-up 1 oscillator period p1 VDD p2 p3 I/O pin Q from port latch n VSS IN1 VSS MBK001 input data b. Standard/quasi-bidirectional. handbook, full pagewidth VDD this diode is not implemented on the I2C-bus pins input data I/O pin VSS MBK002 c. High-impedance input. handbook, full pagewidth strong pull-up VDD VDD p I/O pin Q from port latch n VSS input data VSS MBK003 d. Push-pull. Fig.14 Port configuration options. 2001 Jun 19 31 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.5 Timer 0 and Timer 1 event counters P83CL882 Timer 0 and Timer 1 can perform the following functions: * Measure time intervals and pulse durations * Count events * Measure CPU speed * Generate interrupt requests. Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. Mode 1 16-bit time interval or event counter. Mode 2 8-bit time interval or event counter with automatic reload upon overflow. Mode 3 Timer 1 stopped and Timer 0 operates as two separate counters. A block diagram of Timer 0 and Timer 1 with possible clock sources is shown in Fig.15. Table 37 Timer/counter 0 and Timer/counter 1 related SFRs SFR TCON TMOD SYSCON DESCRIPTION Timer/counter 0 and Timer/counter 1 Control Register Timer/counter 0 and 1 Mode Control Register System Control Register SFR ADDRESS 88H 89H B4H RESET VALUE 0000 0000 0000 0000 0000 0000 f psc f per InstrReq C/T = 0 TL0 T0 TR0 GATE INT0 C/T = 1 control TH0 f psc f per ROMReq C/T = 0 TL1 T1 TR1 GATE INT1 C/T = 1 control MGT292 TH1 Fig.15 Timer/counter 0 and 1; clock sources and control logic. 2001 Jun 19 32 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.5.1 CLOCK SOURCE SIGNALS OF TIMER 0 AND TIMER 1 The four operating modes are: P83CL882 In all four modes Timer 0 and Timer 1 can be configured to increment from different internal and external clock sources. The TMOD and SYSCON registers must be written to determine the source of the clock signal. After reset the clock source for both timers is connected to the internal clock signal from PSC1 (fpsc). The second of four possible clock sources is connected to the other internal clock signal coming from PSC2 (fper). The clock input on both timers has a multiplexer to choose from 4 different clock sources. If the multiplexers are switched to another input by setting user controllable bits in the SYSCON SFR (bits 7 to 4), the timers can also increment on the other on-chip clock signal coming from PSC2 (fper). In counter mode the timers are incrementing on transitions on the T0 and T1 input pins. First way to enter this mode is by setting control bits C/T (TMOD.6 and 2). Second way is to configure SYSCON to switch the input multiplexer to the clock input signal T1 or T0 while C/T is logic 0. The latter is also functional even when there is no system clock available. This means when a clock source is supplied on a port pin the Timer 1 or 0 can count and generate interrupts even when the chip is in Power-down mode. Maximum input signal frequency and duty cycle for the timer in counter mode is given in Chapter 11. The last multiplexer input to Timer 1 and Timer 0 is an auxiliary mode which can be used to obtain the operation speed from the handshake CPU. If this mode is activated for the Timer 1 input source, the timer increments on every ROM request. This means the timer increments by three for a three byte instruction and by two for a two byte instruction etc. If the auxiliary mode is activated for Timer 0 the timer increments on every instruction executed by the CPU. This means the timer register holds the number of instructions executed in a certain time frame. This can be used to obtain the number of Mips at which the processor is running. The SYSCON register is described in Section 6.5.5. 6.5.2 OPERATING MODES OF TIMER 0 AND TIMER 1 Mode 0 Putting either Timer 0 or Timer 1 into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. Figure 16 shows the Mode 0 operation as it applies to Timer 1. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all logic 1s to all logic 0s, it sets the timer interrupt flag TF1. Timer 1 is enabled when TR1 = 1. With GATE = 0, it is continuously counting, setting GATE = 1, the timer is controlled by the external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the SFR TCON (see Section 6.5.3). GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0, and INT0 for the corresponding Timer 1 signals in Fig.16. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Mode 1 Is the same as Mode 0, except that the timer register is being run with all 16 bits. Mode 2 Configures the timer register as an 8-bit counter (TL1) with automatic reload, as shown in Fig.17. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Fig.18. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a timer function and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or in any application not requiring an interrupt. The `Timer' or `Counter' function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1 and M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 configures Timer 0 while Timer 1 is disabled. 2001 Jun 19 33 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 f psc f per ROMReq C/T = 0 TL1 (5 bits) T1 TR1 GATE INT1 C/T = 1 control MGT293 TH1 (8 bits) TF1 interrupt Fig.16 Timer/Counter 0 and 1; Mode 0: 13-bit counter. f psc f per ROMReq C/T = 0 TL1 (8 bits) T1 TR1 GATE INT1 TH1 (8 bits) MGT294 TF1 interrupt C/T = 1 control reload Fig.17 Timer/Counter 0 and 1; Mode 2: 8-bit auto-reload. f psc f per ROMReq C/T = 0 TL0 (8 bits) T0 TR0 GATE INT0 1/12 f osc TF0 interrupt C/T = 1 control TH0 (8 bits) control TR1 TF1 interrupt MGT295 Fig.18 Timer/Counter 0 and 1; Mode 3: two 8-bit counters. 2001 Jun 19 34 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.5.3 TIMER/COUNTER 0 AND 1 CONTROL REGISTER (TCON) P83CL882 Table 38 Timer/Counter 0 and 1 Control Register (SFR address 88H) 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Table 39 Description of TCON bits BIT 7 6 5 4 3 2 1 0 Note 1. If the Timer 0 or Timer 1 is not enabled (TR0 or TR1), the clock to Timer 0/1 is switched off for power saving. 6.5.4 TIMER/COUNTER 0 AND 1 MODE CONTROL REGISTER (TMOD) SYMBOL TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 DESCRIPTION Timer 1 overflow flag. Set by hardware on timer/counter overflow; cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off; note 1. Timer 0 overflow flag. Set by hardware on timer/counter overflow; cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off; note 1. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected; cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software. If IT1 = 1, then external interrupt is LOW-level triggered. If IT1 = 0, then external interrupt is falling edge triggered. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected; cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software. If IT0 = 1, then external interrupt is LOW-level triggered. If IT0 = 0, then external interrupt is falling edge triggered. Table 40 Timer/Counter 0 and 1 Mode Control Register (SFR address 89H) 7 GATE 6 C/T 5 M1 4 M0 3 GATE 2 C/T 1 M1 0 M0 Table 41 Description of TMOD bits BIT 7 6 5 4 3 2 1 0 2001 Jun 19 SYMBOL GATE C/T M1 M0 GATE C/T M1 M0 35 Gating control. When set Timer/Counter 0 is enabled only while INT0 pin is HIGH and TR0 control pin is set; when cleared Timer 0 is enabled whenever TR0 control bit is set. Timer or counter selector. Cleared for timer operation (counts on fPSC); set for counter operation (input from T0 input pin). Timer 0 mode select. See Table 42. DESCRIPTION Gating control. When set Timer/Counter 1 is enabled only while INT1 pin is HIGH and TR1 control pin is set; when cleared Timer 1 is enabled whenever TR1 control bit is set. Timer or counter selector. Cleared for timer operation (counts on fPSC); set for counter operation (input from T1 input pin). Timer 1 mode select. See Table 42. Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Table 42 Timer 0 and Timer 1 mode select n = 0 or 1. M1 0 0 1 1 M0 0 1 0 1 DESCRIPTION 8048-type timer. TLn serves as 5-bit prescaler P83CL882 16-bit Timer/Counter. THn and TLn are cascaded; there is no prescaler 8-bit auto-reload timer/counter. THn holds a value which is to be reloaded into TLn each time it overflows. Timer 0. TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits; TH0 is an 8-bit timer only controlled by Timer 1 control bits. Timer 1. Timer/Counter 1 stopped. 6.5.5 SYSTEM CONTROL REGISTER (SYSCON) Table 43 System Control Register (SFR address B4H; reset value = 0000 0000) 7 T1SRC1 6 T1SRC0 5 T0SRC1 4 T0SRC0 3 - 2 - 1 SELECT 0 XTM Table 44 Description of SYSCON bits BIT 7 6 5 4 3 2 1 0 SYMBOL T1SRC1 T1SRC0 T0SRC1 T0SRC0 - - SELECT XTM comparator select bit; see Section 6.1 oscillator disable bit; see Section 6.1 do not use Timer 0 clock source select bit 1 and 0; see Table 46 DESCRIPTION Timer 1 clock source select bit 1 and 0; see Table 45 Table 45 Timer 1 input source select modes T1SRC1 0 0 1 1 T1SRC0 0 1 0 1 fpsc is the Timer 1 clock input T1 is the Timer 1 clock input the ROMreq signal is the Timer 1 clock input fper is the Timer 1 clock input DESCRIPTION Table 46 Timer 0 input source select modes T0SRC1 0 0 1 1 T0SRC0 0 1 0 1 fpsc is the Timer 0 clock input T0 is the Timer 0 clock input the instruction request signal is the Timer 0 clock input fper is the Timer 0 clock input DESCRIPTION 2001 Jun 19 36 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6 Timer 2 P83CL882 Timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter. Timer 2 has three operating modes: capture, auto-reload up/down counting and clock output mode. The modes are selected using T2CON. 6.6.1 TIMER 2 SPECIAL FUNCTION REGISTERS Timer 2 has six SFRs that can be read and written by the CPU. These registers are: T2CON, T2MOD, T2H, T2L, T2RCH and T2RCL. Timer 2 register values can be changed by hardware or software. If an update by hardware and software occurs in one of the registers T2H, T2L, T2RCH or T2RCL, the update by software has precedence. Table 47 Timer 2 related SFRs SFR T2CON T2MOD T2L T2H T2RCL T2RCH DESCRIPTION Timer 2 Control Register Timer 2 Mode Register Timer 2 Low byte Count Register Timer 2 High byte Count Register Timer 2 Low byte Capture/Reload Register Timer 2 High byte Capture/Reload Register SFR ADDRESS C8H C9H CCH CDH CAH CBH RESET VALUE 00XX 0000 XXXX X000 0000 0000 0000 0000 0000 0000 0000 0000 6.6.1.1 Timer 2 Control Register (T2CON) Table 48 Timer 2 Control Register (SFR address C8H) 7 T2F 6 EXF2 5 - 4 - 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 Table 49 Description of T2CON bits BIT 7 6 SYMBOL T2F EXF2 DESCRIPTION Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when clock out mode is selected. Timer 2 external flag. Set on a negative transition on T2EX and bit EXEN2 = 1. In Auto-reload mode it is toggled on an under- or overflow; this bit must be cleared by software. These 2 bits are reserved each must be set to logic 0. Timer 2 external enable flag. Set by software only; when set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input T2EX if in Capture mode or Auto-reload mode with DCEN reset. If in Auto-reload mode and DCEN is set, the EXEN2 bit has no influence. In the other modes EXF2 is set and an interrupt is generated on a HIGH-to-LOW transition on the T2EX pin. When EXEN2 is reset, Timer 2 ignores events on pin T2EX in all modes. START/STOP control for Timer 2. Set by software only; when set, the timer is started; when reset the timer is stopped. If Timer 2 is not enabled (TR2 = 0), the clock to Timer 2 is switched off for power saving. 1 0 C/T2 CP/RL2 Timer/counter select for Timer 2. Set by software only; when set the counter function is selected, when reset the timer function is selected. Capture/Reload flag. Set by software only; selection of mode capture or reload; when set the capture function is selected, when reset the reload function is selected. 5 and 4 3 - EXEN2 2 TR2 2001 Jun 19 37 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6.1.2 Timer 2 Mode Register (T2MOD) P83CL882 Table 50 Timer 2 Mode Register (SFR address C9H) 7 - 6 - 5 - 4 - 3 - 2 T2RD 1 C/T2OE 0 CP/DCEN Table 51 Description of T2MOD bits BIT 7 to 3 2 SYMBOL - T2RD Reserved; must be kept to logic 0. Timer 2 read flag. Set/reset by hardware only. This bit is set by hardware if a T2L read operation is followed by an increment of T2H before a T2H read operation. This bit is reset on the trailing edge of the next T2L read. This bit is used to indicate that the 16-bit Timer 2 register is not read properly since the T2H part was incremented by hardware before it was read. Timer 2 output enable bit. Set by software only. When set and T2CON.TF2 is reset and T2CON.EXF2 is reset, output T2 outputs a clock signal. When this condition is not met, output T2 outputs a logic 1. The clock output is half the overflow frequency of Timer 2. Down count enable flag. Set by software only. When this bit is set and input T2EX is set Timer 2 can be configured (in Auto-reload mode) as an up counter. When this bit is reset or input T2EX is reset, Timer 2 can be configured (in Auto-reload mode) as a down counter. DESCRIPTION 1 C/T2OE 0 CP/DCEN 6.6.1.3 T2H and T2L Registers These registers are normal registers in the SFR space. They are the actual timer/counter registers. On the fly reading can give a wrong value since T2H can be changed after T2L is read and before T2H is read. This situation is indicated by flag T2RD in T2MOD SFR. In all cases the two 8-bit registers operate as one 16-bit timer/counter register. 6.6.1.4 T2RCH and T2RCL Registers These registers are normal registers in the SFR space. They are the capture and reload registers depending on the chosen operation mode. In the Capture mode the T2RCH/T2RCL registers are loaded with the value of the T2H/T2L registers. In the reload mode the T2H/T2L registers are loaded with the value of the T2RCH/T2RCL registers. 2001 Jun 19 38 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6.2 TIMER 2 MODES IN GENERAL P83CL882 Timer 2 can operate in three different modes: * Capture mode * Auto-reload mode * Clock output mode. In these three modes the timer/counter operates on events detected on inputs T2 and T2EX. Table 52 shows the list of T2CON and T2MOD register bits which set the Timer 2 mode of operation. Sections 6.6.3 to 6.6.5 describe the Timer 2 modes. Table 52 Timer 2 modes CP/RL2 C/T2OE 0 1 0 6.6.3 0 0 1 CAPTURE MODE C/T2 X X 0 OPERATING MODE 16-bit auto-reload 16-bit capture clock output There are two options selected by the T2CON.EXEN2 bit. This bit enables or disables the events of the external trigger input T2EX. * T2CON.C/T2 = 1: Timer 2 is a 16-bit counter. The counter increments at each LOW-to-HIGH transition on input T2 at a maximum rate of one each 12 fpsc cycles. * T2CON.C/T2 = 0: Timer 2 is a 16-bit timer. The timer increments each 6 fPSC cycles. * T2CON.EXEN2 = 1: The external trigger input T2EX is enabled. Timer 2 is a 16-bit timer or counter. - If T2MOD.DCEN = 0, a HIGH-to-LOW transition at input T2EX causes the current Timer 2 value (T2H/T2L data) to be captured into T2RCH/T2RCL, and bit T2CON.EXF2 becomes set. - If T2MOD.DCEN = 1, bit T2CON.EXEN2 has no influence. Overflowing of Timer 2 sets bit T2CON.TF2. * T2CON.EXEN2 = 0: The external trigger input T2EX is disabled. Timer 2 is a 16-bit timer or counter. The T2EX input is ignored. Overflowing of Timer 2 sets bit T2CON.TF2. The Capture mode is shown in Fig.19. In the Capture mode, registers T2RCH/T2RCL are used to capture the T2H/T2L register data. handbook, full pagewidth COMP2L COMP2H ECOMP COMPARATOR 1 (16 BITS) OSC 6 C/T2 = 0 TL2 (8 BITS) T2 pin C/T2 = 1 control TR2 capture transition detector T2EX pin control EXEN2 RCAP2L RCAP2H TH2 (8 BITS) COMP port P1.2 TF2 Timer 2 interrupt EXF2 MBH998 Fig.19 Timer 2 in Capture mode. 2001 Jun 19 39 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6.4 AUTO-RELOAD MODE P83CL882 In the Auto-reload mode, Timer 2 can be configured as a timer or a counter (T2CON.C/T2 bit) and then programmed to count up or down. The counting direction is determined by bit T2MOD.DCEN (down count enable). When reset is applied, then T2MOD.DCEN is reset which defaults to counting up. If T2MOD.DCEN is set, Timer 2 can count up when T2EX = 1 and count down when T2EX = 0. * T2CON.C/T2 = 1: Timer 2 is a 16-bit counter. The counter increments/decrements at each LOW-to-HIGH transition on input T2 at a maximum rate of one each 12 fpsc cycles. * T2CON.C/T2 = 0: Timer 2 is a 16-bit timer. The timer increments/decrements each 6 fpsc cycles. By setting bit T2CON.EXEN2 the external trigger input T2EX is enabled. When resetting bit T2CON.EXEN2, the external trigger input T2EX is disabled. * T2CON.EXEN2 = 1: The external trigger input T2EX is enabled. Timer 2 is a 16-bit timer or counter. A HIGH-to-LOW transition at input T2EX causes the value in T2RCH/T2RCL to be reloaded in the Timer 2 T2H/T2L registers, and bit T2CON.EXF2 becomes set. Also overflowing of Timer 2 causes the value in T2RCH/T2RCL to be reloaded in the T2H/T2L registers and sets bit T2CON.TF2. * T2CON.EXEN2 = 0: The external trigger input T2EX is disabled. Timer 2 is a 16-bit timer or counter. The T2EX input is ignored. Overflowing of Timer 2 causes the value in T2RCH/T2RCL to be reloaded in the T2H/T2L registers and sets bit T2CON.TF2. Timer 2 interrupt will be set if EXF2 is set or TF2 is set. The Auto-reload mode (DCEN = 0) is shown in Fig.20. 6.6.4.1 T2MOD.DCEN = 0: counting up In the Auto-reload mode and counting up, registers T2RCH/T2RCL are used to hold a reload value for T2H/T2L. handbook, full pagewidth COMP2L COMP2H ECOMP COMPARATOR 1 (16 BITS) OSC 6 C/T2 = 0 TL2 (8 BITS) T2 pin C/T2 = 1 control TR2 reload transition detector T2EX pin control EXEN2 RCAP2L RCAP2H TH2 (8 BITS) COMP port P1.2 TF2 Timer 2 interrupt EXF2 MBH999 Fig.20 Timer 2 in Auto-reload mode (DCEN = 0). 2001 Jun 19 40 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6.4.2 T2MOD.DCEN = 1: T2EX = 1: counting up P83CL882 The HIGH value of the external trigger input T2EX sets Timer 2 to a count-up mode. In the Auto-reload mode and counting up, registers T2RCH/T2RCL are used to hold a reload value for T2H/T2L. Overflowing of Timer 2 causes the value in T2RCH/T2RCL to be reloaded in the T2H/T2L registers, sets bit T2CON.TF2 and toggles bit T2CON.EXF2 (T2CON.EXF2 can be used as 17th bit if desired). Timer 2 interrupt will be set if TF2 is set. In the Auto-reload mode and counting down, registers T2RCH/T2RCL are used to hold a value for detecting an underflow of T2H/T2L. Underflow occurs if the contents of T2H/T2L matches the contents of T2RCH/T2RCL. Upon underflow, bit TF2 will be set and registers T2H/T2L will be loaded with FFFFH, bit T2CON.TF2 is set and bit T2CON.EXF2 toggles (T2CON.EXF2 can be used as 17th bit if desired). Note that a Timer 2 roll over from 0000H to FFFFH is not considered as an underflow (only when T2RCH/T2RCL = 0000H). Timer 2 interrupt will be set if TF2 is set. The Auto-reload mode (DCEN = 1) is shown in Fig.21. 6.6.4.3 T2MOD.DCEN = 1: T2EX = 0: counting down The LOW value of the external trigger input T2EX sets Timer 2 to a count down mode. down count reload value toggle FFH FFH EXF2 f psc C/T2 = 0 T2L T2H TF2 Timer 2 interrupt T2 C/T2 = 1 TR2 control T2EX: 1 = count up 0 = count down T2RCL T2RCH MGT296 upcount reload value Fig.21 Timer 2 in Auto-reload mode (DCEN = 1). 2001 Jun 19 41 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.6.5 CLOCK OUTPUT MODE P83CL882 In the Clock output mode, the output T2OUT is enabled as a clock output. A timer overflow will cause T2H/T2L to be loaded with T2RCH/T2RCL and will toggle output T2OUT. The frequency of pin T2OUT is half the overflow frequency. Bit T2CON.EXF2 will be set if T2CON.EXEN2 is set and a HIGH-to-LOW transition is detected on the T2EX pin. Timer 2 interrupt will be set only if T2CON.EXF2 is set. This makes an extra external interrupt available. If Timer 2 does not operate in the Clock output mode, the output T2OUT remains as specified by the I/O SFRs. The Clock output mode is shown in Fig.22. f psc T2L T2H TR2 T2RCL C/ T2 T2OUT T2RCH toggle T2OE Timer 2 interrupt T2EX EXF2 EXEN2 MGT297 Fig.22 Timer 2 in Clock output mode. 2001 Jun 19 42 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.7 Watchdog Timer P83CL882 The Watchdog Timer consists of an 8-bit down counter and a Watchdog prescaler. The binary number defined by bits WD3 to WD0 (WDCON SFR), the Watchdog prescaler and the timer prescaler (fpsc) defines the expiration time of the Watchdog Timer. Once enabled this counter runs continuously. Once expired the timer produces firstly an interrupt and finally a reset. The software must reload the Watchdog Timer at regular intervals to avoid expiration. A positive edge on bit LD (WDCON SFR) (re)loads the counter with the value of WD3 to WD0, sets the LOW bits to logic 1 and activates this counter if it is not yet running. However, to prepare the (re)loading a positive edge must be applied to the COND bit in WDCON. 6.7.1 WATCHDOG TIMER CONTROL REGISTER (WDCON) In this way at least two locations in software are needed before the counter can be reloaded. After reset the counter is not running. Only after the first load (LD) it is clocked continuously by a clock pulse. If the next LD signal is not given within the defined expiration interval an overflow occurs and the processor will be reset (signal WDR). One clock cycle (seen from the Watchdog prescaler output) before the reset is applied a WDI interrupt is issued. This gives the opportunity to avoid the reset if required. The maximum Watchdog Timer expiration time is thus 254/fpsc to the WD interrupt and 255/fpsc to the reset. The WDCON SFR is used to control the operation of the on-chip Watchdog Timer. If the Watchdog Timer is not loaded after reset, the clock to the Watchdog Timer is switched off for power saving. Table 53 Watchdog Timer Control Register (SFR address A5H; reset value = 0000 0000) 7 COND 6 WD3 5 WD2 4 WD1 3 WD0 2 MSKPOL 1 - 0 LD Table 54 Description of WDCON bits BIT 7 6 5 4 3 2 SYMBOL COND WD3 WD2 WD1 WD0 MSKPOL this bit controls the polarity of the input signal to the MSK modem; MSKPOL = 0: input directly connected to the MSK modem MSKPOL = 1: input inverted and connected to the MSK modem 1 0 - LD reserved, must be kept to logic 0 load Watchdog Timer with WD0 to WD3; control signal from CPU DESCRIPTION load condition; control signal from processor WD0 to WD3 is the preset value for the high nibble of the Watchdog Timer 2001 Jun 19 43 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.7.2 WATCHDOG TIMER PRESCALER REGISTER (WDTIM) P83CL882 The WDTIM SFR is used to initialize the prescaler of the on-chip Watchdog Timer. f psc WATCHDOG PRESCALER (WDTIM) WATCHDOG TIMER MGT298 Fig.23 Clocking the Watchdog timer. Table 55 Watchdog Timer Prescaler Register (SFR address A6H; reset value 0000 0000) 7 WDTIM.7 6 WDTIM.6 5 WDTIM.5 4 WDTIM.4 3 WDTIM.3 2 WDTIM.2 1 WDTIM.1 0 WDTIM.0 The expiration time (texp) can be calculated as follows: t exp = ( prescaler factor ) x { 2 + 64 x ( WDTIM + 1 ) } x 16 x ( WDCON + 1 ) x ( clock period ) Where: prescaler factor = the dividing factor from prescaler (PSC1 and PSC2); 1, 2, 4, 6, 8, 10, 12 and 16 WDTIM = the 8-bit value (0 to 255) in the Watchdog Timer Prescaler Register WDCON = the 4-bit value (0 to 15) reloaded in the Watchdog Timer clock period = the period of the signal applied to pin XTAL1. From the texp formulae it follows that the maximum expiration time is: texp(max) = 16 x (2 + 64 x 256) x 16 x (16) x (clock period) = 67 206 016 x (clock period) and the minimum expiration time is: texp(min) = 1 x 66 x 16 x (clock period) = 1056 x (clock period) 6.7.3 EXAMPLE SEQUENCE TO RELOAD THE WATCHDOG TIMER An example of the reload sequence for the Watchdog Timer: MOV WDCON,#00H;Clear COND and LD bit ORL WDCON,#80H;Positive edge WDCON.7, prepare condition ORL WDCON,#01H;Positive edge WDCON.0, reload the timer 2001 Jun 19 44 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.8 I2C-bus serial I/O (master/slave interface) P83CL882 The I2C-bus implements a master/slave I2C-bus interface with integrated shift register, shift timing generation and slave address recognition. I2C-bus standard mode (100 kHz SCLK) and fast mode (400 kHz SCLK) are supported. Low speed mode and extended 10-bit addressing are not supported. The I2C-bus consists of two lines: a data line (SDA) and a clock line (SCL). These lines also function as the I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in 4 modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver. Table 56 I2C-bus related SFRs SFR S1CON S1DAT S1ADR S1STA DESCRIPTION Serial Control Register Data Shift Register Address Register Serial Status Register These functions are controlled by the S1CON register. S1STA is the Serial Status Register whose contents may also be used as a vector to various service routines. S1DAT is the Data Shift Register and S1ADR the Slave Address Register. Slave address recognition is performed by on-chip hardware. The block diagram of the I2C-bus serial I/O is shown in Fig.24. The interface between the CPU and the I2C-bus logic, referred to as `SIO1', is accomplished with four Special Function Registers (see Table 56): The I2C-bus interface is compliant to the specification as described in "The I2C-bus and how to use it" (ordering number 9398 393 40011). This document includes also a detailed description of the I2C-bus protocol. SFR ADDRESS D8H DAH DBH D9H RESET VALUE 0000 0000 0000 0000 0000 0000 1111 1000 2001 Jun 19 45 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.8.1 SERIAL CONTROL REGISTER (S1CON) P83CL882 The CPU can read from and write to this 8-bit SFR. Two bits are affected by the SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C-bus. The STO bit is also cleared when ENS1 = 0. Reset initializes S1CON to 00H. Table 57 Serial Control Register (SFR address D8H) 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0 Table 58 Description of S1CON bits BIT 7 6 SYMBOL CR2 ENS1 DESCRIPTION This bit along with bits CR1 and CR0 determines the serial clock frequency when SIO is in the Master mode; see Table 59. When CR2 = 0 the I2C-bus is in fast mode. ENABLE serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to logic 1; note 1. START flag. When this bit is set in Slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START condition. ENS1 should not be used to temporarily release SIO1 from the I2C-bus since, when ENS1 is reset, the I2C-bus status is lost. The AA flag should be used instead. STOP flag. When the STO bit is set while SIO1 is in a Master mode, a STOP condition is transmitted to the I2C-bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO flag. In a Slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C-bus. However, the SIO1 hardware behaves as if a STOP condition has been received and switches to the defined `not addressed' Slave receiver mode. The STO flag is automatically cleared by the hardware. If the STA and STO bits are both set, the STOP condition is transmitted to the I2C-bus if SIO1 is in a Master mode (in a Slave mode, SIO1 generates an internal STOP condition which is not transmitted). SIO1 then transmits a START condition. When the STO bit is reset, no STOP condition will be generated. 3 SI SIO interrupt flag. This flag is set, and an interrupt is generated, after any of the following events occur: * A start condition is generated in Master mode * Own slave address has been received during AA = 1 * The general call address has been received while S1ADR0 = 1 and AA = 1 * A data byte has been received or transmitted in Master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A STOP or START condition is received as selected slave receiver or transmitter. If this flag is set, the I2C-bus is halted (by pulling down SCL). Received data is only valid until this flag is reset. 5 STA 4 STO 2001 Jun 19 46 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 BIT 2 SYMBOL AA DESCRIPTION Assert acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * General call address is received (S1ADR.0 = 1) * A data byte is received while the device is programmed to be a master receiver * A data byte is received while the device is a selected slave receiver. When SIO1 is in the addressed Slave transmitter mode, state C8H will be entered after the last serial bit is transmitted. When SI is cleared, SIO1 leaves state C8H, enters the not addressed Slave receiver mode, and the SDA line remains at a HIGH level. In state C8H, the AA flag can be set again for future address recognition. When SIO1 is in the not addressed Slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, SIO1 can be temporarily released from the I2C-bus while the bus status is monitored. While SIO1 is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the parts own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission. When this bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own slave address or general call address is received. 1 0 Note CR1 CR0 These two bits along with the CR2 bit determine the serial clock frequency when SIO is in the Master mode; see Table 59. 1. If the serial I/O is not enabled (ENS1), the clock to the serial I/O is switched off for power saving. Table 59 Selection of the serial clock frequency in the Master mode of operation Bit rates greater than 400 kHz are outside the specified frequency range. CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fper DIVISOR 10 20 30 40 80 120 160 not valid selection BIT RATE (kHz) AT fper 3.58 MHz 358 179 119.33 89.5 44.75 29.83 22.38 - 4 MHz 400 200 133 100 50 33 25 - 6 MHz (600) 300 199.5 150 75 49.5 37.5 - 2001 Jun 19 47 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.8.2 DATA SHIFT REGISTER (S1DAT) P83CL882 S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from and write to this 8-bit SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag is set. Data in S1DAT remains stable as long as SI is set. Data in S1DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7) and after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. Reset initializes S1DAT to 00H. S1DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit byte, followed by an acknowledge bit. Table 60 Data Shift Register (SFR address DAH) 7 S1DAT.7 6 S1DAT.6 5 S1DAT.5 4 S1DAT.4 The ACK flag is controlled by the SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK flag into S1DAT on the rising edges of clock pulses on the SCL line. When a byte has been shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit is returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT via a buffer on the falling edges of clock pulses on the SCL line. When the CPU writes to S1DAT, the buffer is loaded with the contents of S1DAT.7 which is the first bit to be transmitted to the SDA line. After nine serial clock pulses, the eight bits in S1DAT will have been transmitted to the SDA line, and the acknowledge bit will be present in ACK. Note that the eight transmitted bits are shifted back into S1DAT. 3 S1DAT.3 2 S1DAT.2 1 S1DAT.1 0 S1DAT.0 Table 61 Description of S1DAT bits BIT 7 to 1 SYMBOL S1DAT.[7:0] DESCRIPTION Eight data bits, to be transmitted or just received. A logic 1 in S1DAT corresponds to a HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW level on the bus. Serial data transmission of S1DAT is MSB first. 2001 Jun 19 48 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.8.3 ADDRESS REGISTER (S1ADR) P83CL882 The CPU can read from and write to this 8-bit SFR. S1ADR is not affected by the SIO1 hardware. The contents of this register are irrelevant when SIO1 is in a Master mode. In the Slave modes, the seven most significant bits must be loaded with the microcontrollers own slave address, and, if the least significant bit is set, the general call address (00H) is recognized; otherwise it is ignored. Reset initializes S1ADR to 00H. Table 62 Address Register (SFR address DBH) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 GC Table 63 Description of S1ADR bits BIT 7 to 1 SYMBOL SLA[6:0] DESCRIPTION These bits correspond to the 7-bit slave address which will be recognized on the incoming data stream from the I2C-bus; when the slave address is detected and the interface is enabled, a serial interrupt will be generated to the CPU. This bit is used to determine whether the general CALL address is recognized. When a logic 0, the general CALL address is not recognized; when a logic 1, the general CALL address is recognized. 0 GC 6.8.4 SERIAL STATUS REGISTER (S1STA) S1STA is an 8-bit read-only Special Function Register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When S1STA contains F8H, no relevant state information is available and no serial interrupt is requested. Reset initializes S1STA to F8H. All other S1STA values correspond to defined SIO1 states. When each of these states is entered, a serial interrupt is requested (SI = 1). The status codes for all possible modes of the I2C-bus interface are given in Table 66. The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. S1STA is a read-only register. Table 64 Serial Status Register (SFR address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0 Table 65 Description of S1STA bits BIT 3 to 7 0 to 2 SYMBOL SC[4:0] - 5-bit status code these three bits are held LOW DESCRIPTION 2001 Jun 19 49 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Table 66 Status codes for the different modes S1STA VALUE MST/TRX mode 08H 10H 18H 20H 28H 30H 38H a START condition has been transmitted a repeated START condition has been transmitted SLA and W have been transmitted, ACK has been received SLA and W have been transmitted, ACK received DATA of S1DAT has been transmitted, ACK received DATA of S1DAT has been transmitted, ACK received arbitration lost in SLA, R/W or DATA DESCRIPTION P83CL882 MST/REC mode 38H 40H 48H 50H 58H arbitration lost while returning ACK SLA and R have been transmitted, ACK received SLA and R have been transmitted, ACK received DATA has been received, ACK returned DATA has been received, ACK returned SLV/REC mode 60H 68H 70H 78H 80H 88H 90H 98H A0H own SLA and W have been received, ACK returned arbitration lost in SLA, R/W as MST; own SLA and W have been received, ACK returned general CALL has been received, ACK returned arbitration lost in SLA, R/W as MST; general CALL has been received previously addressed with own SLA; DATA byte received, ACK returned previously addressed with own SLA; DATA byte received, ACK returned previously addressed with general CALL; DATA byte has been received, ACK has been returned previously addressed with general CALL; DATA byte has been received, ACK has been returned a STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX SLV/TRX mode A8H B0H B8H C0H C8H own SLA and R have been received, ACK returned arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned DATA byte has been transmitted, ACK received DATA byte has been transmitted, ACK received last DATA byte has been transmitted (AA = 0), ACK received Miscellaneous 00H F8H bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition no information available (reset value). The serial interrupt flag SI, is not yet set 2001 Jun 19 50 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Table 67 Symbols used in Table 66 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 6.8.5 7-bit slave address Read bit Write bit acknowledgement (acknowledge bit = logic 0) no acknowledgement (acknowledge bit = logic 1) 8-bit data byte to or from I2C-bus master slave transmitter receiver DESCRIPTION P83CL882 MODES OF OPERATION The I2C-bus logic may operate in any of the following four modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver. As a master, the I2C-bus logic will generate all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I2C-bus will not be released. Two types of data transfers are possible on the I2C-bus: * Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. * Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after each received byte except the last byte. At the end of the last received byte, a `not acknowledge' is returned. In a given application, SIO1 may operate as a master and as a slave. In the Slave mode, the SIO1 hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the Master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the Master mode, SIO1 switches to the Slave mode immediately and can detect its own slave address in the same serial transfer. 6.8.5.1 Master transmitter mode Serial data is output through SDA while SCL outputs the serial clock. The first byte transmitted contains the slave address (7-bit SLA) of the receiving device and the data direction bit. In this case the data direction bit (R/W) will be a logic 0 (W). Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In the Master transmitter mode, a number of data bytes can be transmitted to the slave receiver. Before the Master transmitter mode can be entered, S1CON must be initialized with the ENS1 bit set and the STA, STO and SI bits reset. ENS1 must be set to enable the SIO1 interface. If the AA bit is reset, SIO1 will not acknowledge its own slave address or the general call address if they are present on the bus. This will prevent the SIO1 interface from entering a Slave mode. 2001 Jun 19 51 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller The Master transmitter mode may now be entered by setting the STA bit. The SIO1 logic will then test the I2C-bus and generate a start condition as soon as the bus becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set, and the status code in the Status Register (S1STA) will be 08H. This status code must be used to vector to an interrupt service routine that loads S1DAT with the slave address and the data direction bit (SLA + W). The SI bit in S1CON must then be reset before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes in S1STA are possible. The appropriate action to be taken for any of the status codes is detailed in the table. After a repeated start condition (state 10H), SIO1 may switch to the Master receiver mode by loading S1DAT with SLA + R. P83CL882 recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. In the slave receiver mode, a number of data bytes are received from a master transmitter. To initiate the Slave receiver mode, S1ADR must be loaded with the 7-bit slave address to which SIO1 will respond when addressed by a master. Also the least significant bit of S1ADR should be set if the interface should respond to the general call address (00H).The Serial Control Register (S1CON) should be initialized with ENS1 and AA set and STA, STO, and SI reset in order to enter the Slave receiver mode. Setting the AA bit will enable the logic to acknowledge its own slave address or the general call address and ENS1 will enable the interface. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be logic 0 (W) for SIO1 to operate in the Slave receiver mode. After its own slave address and the W bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from S1DAT. This status code should be used to vector to an interrupt service routine, and the appropriate action to be taken for each of the status codes is detailed in Table 66. The Slave receiver mode may also be entered if arbitration is lost while SIO1 is in the Master mode. If the AA bit is reset during a transfer, SIO1 will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C-bus is still monitored and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C-bus. 6.8.5.2 Master receiver mode The first byte transmitted contains the slave address of the transmitting device (7-bit SLA) and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (R). Serial data is received via SDA while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial transfer. In the Master receiver mode, a number of data bytes are received from a slave transmitter. The transfer is initialized as in the Master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load S1DAT with the 7-bit slave address and the data direction bit (SLA + R). The SI bit in S1CON must then be cleared before the serial transfer can continue. When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a number of status codes are possible in S1STA. The appropriate action to be taken for each of the status codes is detailed in the table. After a repeated start condition (state 10H), SIO1 may switch to the Master transmitter mode by loading S1DAT with SLA + W. 6.8.5.4 Slave transmitter mode The first byte is received and handled as in the Slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In the Slave transmitter mode, a number of data bytes are transmitted to a master receiver. Data transfer is initialized as in the Slave receiver mode. When S1ADR and S1CON have been initialized, SIO1 waits until it is addressed by its own slave address followed by the data direction bit which must be logic 1 (R) for SIO1 to operate in the Slave transmitter mode. 6.8.5.3 Slave receiver mode Serial data and the serial clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are 2001 Jun 19 52 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller After its own slave address and the R bit have been received, the serial interrupt flag (SI) is set and a valid status code can be read from S1STA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in the table. The Slave transmitter mode may also be entered if arbitration is lost while SIO1 is in the Master mode. If the AA bit is reset during a transfer, SIO1 will transmit the last byte of the transfer and enter state C0H or C8H. SIO1 is switched to the not addressed Slave mode and will ignore the master receiver if it continues the transfer. Thus the master receiver receives all logic 1s as serial data. While AA is reset, SIO1 does not respond to its own slave address or a general call address. However, the I2C-bus is still monitored, and address recognition may be resumed at any time by setting AA. This means that the AA bit may be used to temporarily isolate SIO1 from the I2C-bus. 6.8.6 FUNCTIONAL DESCRIPTION I2C-BUS INTERFACE P83CL882 A slave may stretch the space duration to slow down the bus master. The space duration may also be stretched for handshaking purposes. This can be done after each bit or after a complete byte transfer. SIO1 will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. The serial interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is cleared. This block also controls all of the signals for serial byte handling. It provides the shift pulses for S1DAT, enables the comparator, generates and detects START and STOP conditions, receives and transmits acknowledge bits, controls the Master and Slave modes, contains interrupt request logic and monitors the I2C-bus status. 6.8.6.3 Bus clock generator 6.8.6.1 Input filter Input signals SDA and SCL from I/O pad cells are synchronized with fper, and spikes shorter than three clock periods are filtered out. This programmable clock pulse generator provides the SCL clock pulses when SIO1 is in the Master transmitter or Master receiver mode. It is switched off when SIO1 is in a Slave mode. The output frequency is dependent on the CR bits in the control register. The output clock pulses have a 50% duty cycle unless the clock generator is synchronized with other SCL clock sources as described above. 6.8.6.2 Arbitration and control logic 6.8.6.4 Address Register (S1ADR) and comparator In the Master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C-bus. If another device on the bus overrules a logic 1 and pulls the SDA line LOW, arbitration is lost, and SIO1 immediately changes from master transmitter to slave receiver. SIO1 will continue to output clock pulses (on SCL) until transmission of the current serial byte is complete. Arbitration may also be lost in the Master receiver mode. Loss of arbitration in this mode can only occur while SIO1 is returning a `not acknowledge' (logic 1) to the bus. Arbitration is lost when another device on the bus pulls this signal LOW. Since this can occur only at the end of a serial byte, SIO1 generates no further clock pulses. The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the `mark' duration is determined by the device that generates the shortest `marks,' and the `space' duration is determined by the device that generates the longest `spaces'. This 8-bit SFR may be loaded with the 7-bit slave address to which SIO1 will respond when programmed as a slave. The least significant bit is used to enable the general call address recognition. The comparator compares the received 7-bit slave address with its own slave address. It also compares the first received byte with the general call address. If an equality is found, the appropriate status bits are set and an interrupt is requested. 6.8.6.5 Data Shift Register (S1DAT) This 8-bit SFR contains a byte of serial data to be transmitted or a byte which has just been received. Data in S1DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7) and, after a byte has been received, the first bit of received data is located at the MSB of S1DAT. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 2001 Jun 19 53 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.8.6.6 Serial Control Register (S1CON) P83CL882 This 8-bit SFR is used by the microcontroller to control the generation of START and STOP conditions, enable the interface, control the generation of ACKs, and to select the clock frequency. 6.8.6.7 Serial Status Register (S1STA) The status decoder takes all of the internal status bits and compresses them into a 5-bit code. This code is unique for each I2C-bus status. The 5-bit code may be used to generate vector addresses for fast processing of the various service routines. Each service routine processes a particular bus status. There are 26 possible bus states if all four modes of SIO1 are used. The 5-bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. The three least significant bits of the Serial Status Register are always zero. If the status code is used as a vector to service routines, then the routines are displaced by eight address locations. Eight bytes of code should be sufficient for most of the service routines. handbook, full pagewidth SLAVE ADDRESS GC S1ADR SDA SHIFT REGISTER INTERNAL BUS S1DAT ARBITRATION LOGIC SCL BUS CLOCK GENERATOR 7 S1CON 6 5 4 3 2 1 0 7 S1STA 6 5 4 3 2 1 0 MBC749 - 1 Fig.24 Block diagram of I2C-bus serial I/O. 2001 Jun 19 54 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9 MSK modem P83CL882 The MSK modem is used for in-band signalling between handset and base in analog cordless telephone systems CT0, CT1 and CT1+. The MSK modems receiver and transmitter can be enabled separately. Receive and transmit interrupts can wake-up the microcontroller during its power saving Idle mode. Baud rates are programmable. Figure 25 shows the functional diagram of the MSK modem. The modem has the following features: * Full-duplex operation via an 8-bit parallel interface * The message is fully Manchester coded/decoded * Automatic detection of 16-bit Manchester preamble pattern * The last received 4 bits of the preamble pattern are software programmable * Receiver full, transmitter empty indication bits * Manchester coding and decoding for clock recovery and early error detection * Programmable input polarity (see WDCON SFR; Section 6.7.1) * Baud rate selection of 1/2976fper, 2/2976fper, 3/2976fper and 4/ 2976fper * Receiver and transmitter off states with no power consumption. Px.x(1) MCLK 80C51 CORE MRI MTI IBD (7-0) AN (7-0) Py.y(1) MB1,2 TIMER MCON MSTAT MTEN MPR MREN MOUT0 RECEIVER TRANSMITTER MOUT1 MOUT2 R0 R1 R2 MBUF MSK MODEM TELX MICROCONTROLLER RX_MUTE MIN SLICER RF RF VOUT TX_MUTE earpiece mouthpiece MGU221 (1) The signals RX_MUTE and TX_MUTE are handled by software. Any available output pin can be used. Fig.25 MSK modem functional diagram. 2001 Jun 19 55 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.1 80C51 MICROCONTROLLER INTERFACE P83CL882 The MSK modem block interfaces to the microcontroller via the interrupt signals MRI and MTI and via the control and data SFRs MCON, MSTAT and MBUF. The MSK modem receive and transmit registers are both accessed via the Special Function Register MBUF. Writing to MBUF loads the transmit register and reading MBUF accesses a physically separate receive register. Table 68 MSK modem related SFRs SFR MCON MSTAT MBUF DESCRIPTION MSK Modem Control Register MSK Modem Status Register MSK Modem Data Buffer SFR ADDRESS D3H D2H D1H RESET VALUE 0000 0000 XX00 0000 0000 0000 6.9.1.1 MSK Modem Control Register (MCON) Table 69 MSK Modem Control Register (SFR address D3H) 7 MPR3 6 MPR2 5 MPR1 4 MPR0 3 MB1 2 MB0 1 MTEN 0 MREN Table 70 Description of MCON bits BIT 7 6 5 4 3 2 1 SYMBOL MPR3 MPR2 MPR1 MPR0 MB1 MB0 MTEN Modem transmit/receive frequency. These 2 bits define the modem transmit/receive frequency; see Table 71. Modem Transmitter Enable. If this bit is set the transmitter is active and MOUT[2:0] will get the value `100' if no data is transmitted. If reset, MOUT[2:0] will get the value `111' to zero the currents in the resistive DAC; see note 1. Modem Receiver Enable. If this bit is set the modem receiver is active and scans for Manchester data; see note 1. DESCRIPTION Modem preamble pattern. These 4 bits define the modems preamble pattern. 0 Note MREN 1. If both the transmitter and the receiver are disabled (MTEN = 0 and MREN = 0), the clock of the MSK modem is switched off. It is advised to use this state for power saving. Table 71 Selection of the modems baud rates MB1 0 0 1 1 MB0 0 1 0 1 MODEM BAUD RATE 1/ 2/ 3/ 4/ 2976fper 2976fper 2976fper 2976fper 2001 Jun 19 56 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.1.2 MSK Modem Status Register (MSTAT) P83CL882 Table 72 MSK Modem Status Register (SFR address D2H) 7 - 6 - 5 MRF 4 MRE 3 MRP 2 MRL 1 MTI 0 MRI Table 73 Description of MSTAT bits BIT 5 SYMBOL MRF DESCRIPTION Modem Receiver Full flag. MRF is set when MBUF holds a newly received byte. MRF is reset if the receiver is disabled (MREN = 0) or by clearing MRI. This bit is read-only; writing to it will have no effect. Modem Receiver Error flag. Indicates the reception of a non-Manchester bit. This bit is set by hardware and is reset by disabling the receiver (MREN = 0) or by clearing MRI. This bit is read-only; writing to it will have no effect. Modem Receiver Preamble flag. MRP is set by hardware when the modem recognizes the programmed preamble pattern (AAAH) after locking the receiver clock (MRL = 1). MRP is reset by hardware if the receiver is disabled (MREN = 0) or if non-Manchester data is received (MRE = 1). This bit is read-only; writing to it will have no effect. Modem Receiver Clock Locked flag. This bit is set when the clock of the receiver is locked, i.e. when the receiver has detected three consecutive Manchester bits but has not found the preamble pattern yet. MRL is reset when the receiver detects a non-Manchester bit or when the receiver is disabled. This bit is read-only; writing to it will have no effect. Modem Transmit Interrupt flag. Indicates MBUF is empty and ready to accept a new byte for transmission. MTI is reset by writing a logic 0 to it. Writing a logic 1 to MTI sets the bit and allows a hardware interrupt to be generated by software. Modem Receive Interrupt flag. Indicates: Modem Receiver Full (MRF = 1) or Modem Receiver Error (MRE = 1) or Modem Receiver Preamble (MRP = 1) or Modem Receiver Clock Locked (MRL = 1). This bit is reset by writing a logic 0 to MRI. A reset of MRI will also reset MRE. Writing a logic 1 to MRI will have no effect. 4 MRE 3 MRP 2 MRL 1 MTI 0 MRI 6.9.1.3 MSK Modem Data Buffer (MBUF) Table 74 MSK Modem Data Buffer (SFR address D1H) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Table 75 Description of MBUF bits BIT 7 to 0 SYMBOL D7 to D0 DESCRIPTION Writing to MBUF loads the data into the transmit buffer and starts a transmission at MOUT if the transmitter is enabled (MTEN = 1). A new byte can be loaded after MTI is set. If a new byte is loaded before MTI is set the previous byte will be lost. After data has been received at MIN, indicated by MRI, the received byte can be read from MBUF. 2001 Jun 19 57 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.2 MODEM INTERFACE P83CL882 The modem block has the following modem interface signals, * MIN: MSK Manchester coded input signal from the data slicer * MOUT0 to MOUT2: 3-bit Manchester coded output signal of the modem. The MSK receiver input can be inverted by programming bit MSKPOL (WDCON.2; see Section 6.7.1): * MSKPOL = 0: direct connection between the MIN pin and MSK receiver * MSKPOL = 1: inverted connection between the MIN pin and MSK receiver. The mute signals RX_MUTE and TX_MUTE must be handled by software according to the progress in the data transfer. Any standard I/O port pin can be used for this purpose. 6.9.3 SYNCHRONISATION If these three sets have been found the clock is locked (MRL = 1) and the receiver starts looking for the Manchester preamble pattern. From this point on the receiver uses a Phase-Locked Loop (PLL) to adjust the synchronisation after each received Manchester bit. To detect a sample shift the receiver uses all 8 samples. If the data is at maximum, one sample out of phase, the receiver is able to resynchronize without losing data. If the data is up to three samples out of phase the receiver can still resynchronize but the data is lost. The correction is done by shifting only one sample per bitcell. This means up to three bit cells are needed for full resynchronisation. If the receiver is not able to establish resynchronization within three bitcells the lock bit (MRL) will be reset. Therefore the MSK modem can receive correct input data with maximum jitter of 1/fsample. MIN MIN When enabled the receiver samples MIN with a frequency fsample = 8 x baud rate. The sampled values are shifted into an 8-bit shift register. This register is regularly checked to determine whether it contains samples that fulfil the Manchester coding rule, i.e. whether there is a LOW-to-HIGH or a HIGH-to-LOW transition in the middle of the bitcell. Figure 26a shows a regular, full synchronized bitcell. Figure 26b shows a regular, not synchronized bitcell, this phase shift will be corrected in the next received bitcell. Figure 26c (data is faster than internal timebase) and Fig.26d (data is slower than internal timebase) represent a non-valid, not synchronized bitcell. In the next received bitcell the data will be re-synchronized but the current data bit does not fulfil the Manchester coding rule and will be lost. The receiver searches for three consecutive sets of 8 samples that fulfil the Manchester coding rule. 12345678 (a) 12345678 (b) MIN MIN 12345678 (c) 12345678 (d) MGT299 Fig.26 Schematic representation of a bitcell. 2001 Jun 19 58 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.4 DATA RECEPTION P83CL882 A message is received as a block of one or more data bytes. When enabled, the receiver starts sampling MIN and tries to detect a Manchester pattern. As soon as 3 consecutive Manchester bits are detected the receiver clock is locked (MRL = 1) and the receiver starts scanning the incoming data for the programmed Manchester preamble pattern. When the modem recognizes the preamble pattern, bit MRP is set to a logic 1. If a non-Manchester bit is detected before finding the preamble pattern then MRL is reset and MRE is set to a logic 1. The synchronisation process has to restart. If the preamble pattern has been detected the receiver starts to Manchester decode the incoming data bits and shifts them into an internal register. After 8 bits the contents of the internal register are copied to MBUF and the MRF bit is set to a logic 1. The received byte can be read from MBUF while receiving continues in the internal register. If a non-Manchester bit is received during data reception then MRE is set to a logic 1 and MRL and MRP are reset. The receiver has to resynchronize before receiving new data. Whenever one of the bits MRF, MRE, MRP and MRL is set the MRI bit is also set and a MSK receive interrupt is generated. This means that when a MSK receive interrupt occurs the 4 status bits have to be polled by software. The bit MRL allows the software to decide very quickly whether an occupied channel contains Manchester coded data or not. The MRP bit is used to find the start of data transmission in a message that is repeated over and over again. MRE is used to detect a Manchester error, which is a violation of the Manchester coding rule that the received level should change in the middle of a bitcell. The MRF bit indicates that the data in MBUF is ready to be read by the software. During data reception the minimum time between two settings of MRF (each one generating an MRI interrupt) is: 8 t min = -----------------------baud rate Figure 27 shows an example of the data reception timing diagram. write MREN = 1 80C51 access MIN no Manchester code: speech?? data 37 clear RTI read read clear MBUF MBUF 1F 37 RTI clear RTI data AA data AD data 1F data 37 no Manchester code: speech?? MRI MRL MRP MRE MRF RX_MUTE should be generated by microcontroller upon interrupt RX_MUTE should be cleared by microcontroller at end of message MGU222 Fig.27 Data reception timing diagram. 2001 Jun 19 59 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.5 DATA TRANSMISSION P83CL882 Data transmission is enabled if bit MTEN in register MCON is set to a logic 1. If MTEN is a logic 0, data transmission is disabled and MOUT[2:0] is set to `111' to zero the currents in the resistive DAC. Setting MTEN to a logic 1 sets MOUT[2:0] to the idle value `100'. This results in a value close to 1/2VDD on the output signal of the external DAC. Transmission is started by loading the first byte into register MBUF. All bytes are transmitted starting with the MSB. A message is transferred in a block of 3 or more bytes, the first two bytes being the programmed Manchester preamble pattern. In order to insert the preamble pattern, the first two bytes AAH and AxH (with `x' being the MPR3 to MPR0 value programmed in the receiver MSK modem) have to be written to MBUF by software. After this, the first byte of the message is written to MBUF. As soon as MBUF is ready to accept new input, signal MTI is set. The minimum time between two MTI interrupts is: 8 t min = -----------------------baud rate If no new byte is written to MBUF at the end of a byte transmission, the modem transmitter stops transmission and MOUT[2:0] is set to the idle state `100'. MTI must be cleared explicitly. If MTEN is reset during transmission, the transmitter will finish the transmission of the current byte and then will set MOUT[2:0] to the off state `111'. No interrupt on MTI will be generated at the end of the transmission. handbook, full pagewidth 80C51 access write write set MBUF MBUF MTEN AAH ADH write MBUF AAH write MBUF 55H write MBUF 55H clear MTI MOUT data AAH data ADH data AAH data 55H data 55H MTI TX_MUTE MGK229 Fig.28 Data transmission timing diagram. 2001 Jun 19 60 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.9.6 WAVEFORM GENERATION WITH MOUT[2:0] P83CL882 The 3 digital output pins MOUT0 to MOUT2, should be used as an input to a 3-bit external DAC. The signals can be connected via external resistors R0, R1 and R2 to a summation point and then be filtered with an external capacitor (C1). The 3-bit DAC is shown in Fig.29. Table 76 gives the relationship between the MOUT pins and VOUT. Figure 30 shows the waveforms that are produced by the waveform generator. The horizontal axis shows the sample counter on which the waveform changes its value. Each bit is built-up out of 2 x 124 samples. The vertical axis shows the values of MOUT[2:0], forming the inputs of the resistive DAC. The first half of the waveform is determined by the previous and the current bit, whereas the second half of the waveform is determined by the current and the next bit to be transmitted. The count frequency of the sample counter depends on the programmed baud rate. If the transmitter is disabled with MTEN set to a logic 0, MOUT[2:0] is `111' to save power in the resistive DAC. If the transmitter is enabled and no data is transmitted, MOUT[2:0] has an idle value of `100', which corresponds to 0.57VDD. Table 76 VOUT as a function of MOUT[2:0] MOUT2 0 0 0 0 1 1 1 1 Note 1. VOUT with resistor values (see Fig.29): R1 = 0.5R0; R2 = 0.25R0 MOUT1 0 0 1 1 0 0 1 1 MOUT0 0 1 0 1 0 1 0 1 VOUT(1) 0 0.14VDD 0.29VDD 0.43VDD 0.57VDD 0.71VDD 0.86VDD VDD handbook, halfpage MOUT0 WAVEFORM GENERATOR MOUT1 MOUT2 R0 R1 R2 C1 = 10 nF MGK231 VOUT Fig.29 3-bit DAC with MOUT[2:0]. 6.9.7 MANCHESTER CODING OF DATA The bits of the data byte written in MBUF are Manchester encoded as shown in Fig.30. A logic 1 is coded as a LOW-to-HIGH transition in the middle of a bitcell, a logic 0 is coded as a HIGH-to-LOW transition.The Manchester encoded signal contains redundancy for early error detection in received bits. A non-matching HIGH-to-LOW or LOW-to-HIGH pair indicates an error condition.The Manchester encoded signal has a polarity change in each bitcell. 2001 Jun 19 61 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 handbook, full pagewidth 111 MGK232 110 101 100 011 010 001 000 11 111 110 101 100 011 010 001 000 11 111 110 101 100 011 010 001 000 11 111 110 101 100 011 010 001 000 11 111 110 101 100 011 010 001 000 43 111 110 101 100 011 010 001 000 43 111 110 101 100 011 010 001 000 43 111 110 101 100 011 010 001 000 43 24 41 24 41 24 41 24 41 000 84 100 113 124 11 24 41 84 100 113 124 001 84 100 113 124 23 48 81 124 110 84 100 113 124 23 48 81 124 111 84 100 113 124 11 24 41 84 100 113 124 100 76 101 124 11 24 41 84 100 113 124 101 76 101 124 23 48 81 124 010 76 101 124 23 48 81 124 011 76 101 124 11 24 41 84 100 113 124 Fig.30 Waveforms with MOUT[2:0] for previous, current and next bits to be transmitted. 2001 Jun 19 62 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 6.10 Internal Data Memory P83CL882 Internal Data Memory is mapped in Fig.31. The memory space is divided into three blocks, which are referred to as the lower 128, the upper 128, and SFR space. Internal Data Memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes, using a simple trick. Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus Fig.31 shows the upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. The lower 128 bytes of RAM are present in all 80C51 devices as mapped in Fig.32. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the lower 128 can be accessed by either direct or indirect addressing. The upper address space of 128 bytes is overlaid with the 128-byte SFR address space. When using indirect addressing the internal data memory is accessed but when using direct addressing the SFR memory space is accessed. Figure 31 shows the overlay of internal Data Memory and SFR memory space. SFRs include the Port latches, timers, peripheral controls, etc. Sixteen addresses in SFR space are both byte-and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H. 7FH In the 83CL882 only 128 bytes of RAM are implemented, therefore the upper 128 bytes are mapped to the lower memory block 2FH FFH upper 128 80H 7FH lower 128 0 Accessible by Direct and Indirect Addressing Accessible by Indirect Addressing only Accessible by Direct Addressing 80H Ports, Status and Control Bits, Timers, Registers, Stack Pointer, Accumulator, etc. FFH bank select bits in PSW 11 bit-addressable space (bit addresses 0 to 7FH) 20H 1FH 18H 17H 10 10H 0FH 01 08H 07H 00 0 MGT303 SFR Memory Space 4 banks of 8 registers R0 to R7 reset value of Stack Pointer MBL261 RAM data memory Fig.31 Internal Data Memory. Fig.32 The lower 128 bytes of internal Data Memory. 2001 Jun 19 63 6.11 Special Function Registers overview 2001 Jun 19 64 Philips Semiconductors 80C51 Ultra Low Power (ULP) telephony controller Table 77 SFRs overview An empty field (-) indicates a bit that can be read or written to by software. ADDR BIT R/W (HEX) ADDRESSABLE 80 81 82 83 87 88 89 8A 8B 8C 8D 8E 8F 90 9E 9F A5 A6 A8 B0 B4 B8 BE BF C0 C8 C9 CA RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW yes - - - - yes - - - - - - - yes - - - - yes yes - yes - - yes yes - - NAME P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P0CFGA P0CFGB P1 P1CFGA P1CFGB WDCON WDTIM IEN0/IE P3 IP0 P3CFGA P3CFGB IRQ1 T2CON T2MOD T2RCL 7 - - - - - TF1 GATE - - - - - - - - - COND - EA - - - - IQ9 T2F - - 6 - - - - - TR1 C/T - - - - - - - - - WD3 - ET2 - PT2 - - IQ8 EXF2 - - 5 - - - - - TF0 M1 - - - - - - - - - WD2 - ES1 - PS1 - - IQ7 - - - 4 - - - - - TR0 M0 - - - - - - - - - WD1 - - - T0SRC0 - - - IQ6 - - - 3 - - - - - IE1 GATE - - - - - - - - - WD0 - ET1 - - PT1 - - IQ5 EXEN2 - - 2 - - - - - IT1 C/T - - - - - - - - - MSKPOL - EX1 - - PX1 - - IQ4 TR2 T2RD - 1 - - - - PD IE0 M1 - - - - - - - - - - - ET0 - SELECT PT0 - - IQ3 C/T2 C/T2OE - 0 - - - - IDL IT0 M0 - - - - - - - - - LD - EX0 - XTM PX0 - - IQ2 CP/RL2 CP/DCEN - RESET VALUE EFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H F3H 00H FFH FFH 00H 00H 00H 00H FFH 00H 00H FFH 00H 00H 00H 00H 00H SYSCON T1SRC1 T1SRC0 T0SRC1 Product specification P83CL882 2001 Jun 19 65 Philips Semiconductors ADDR BIT R/W (HEX) ADDRESSABLE CB CC CD D0 D1 D2 D3 D8 D9 DA DB DD E0 E1 E8 E9 F0 F1 F3 F8 F9 Notes 1. This bit is read only. RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW - - - yes - - - yes - - - - yes - yes - yes - - yes - NAME T2RCH T2L T2H PSW MBUF MSTAT MCON S1CON S1STA S1DAT S1ADR WKCON ACC ISE1 IEN1 IX1 B IEN2 PRESC IP1 IP2 7 - - - CY D7 - MPR3 CR2 SC4 - SLA6 - - ISE9 EX9 IX9 - EWDI PX7 PWDI 6 - - - AC D6 - MPR2 ENS1 SC3 - SLA5 - - ISE8 EX8 IX8 - EADI PX6 PADI 5 - - - F0 D5 MRF(1) MPR1 STA SC2 - SLA4 - - ISE7 EX7 IX7 - EKPI SYNC PX5 PKPI 4 - - - RS1 D4 MRE(1) MPR0 STO SC1 - SLA3 - - ISE6 EX6 IX6 - - - PX6 - 3 - - - RS0 D3 MRP(1) MB1 SI SC0 - SLA2 - - ISE5 EX5 IX5 - ELVD - PX5 PLVD 2 - - - OV D2 MRL(1) MB0 AA 0 - SLA1 - - ISE4 EX4 IX4 - - - PX4 - 1 - - - - D1 MTI MTEN CR1 0 - SLA0 - - ISE3 EX3 IX3 - EMTI - PX3 PMTI 0 - - - P(1) D0 MRI(2) MREN CR0 0 - GC - - ISE2 EX2 IX2 - EMRI - PX2 PMRI RESET VALUE 00H 00H 00H 00H 00H 00H 00H 00H F8H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 80C51 Ultra Low Power (ULP) telephony controller EXTCK AUXSW 2. This bit is set to logic 1 by hardware; can only be cleared by software. Product specification P83CL882 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 7 INSTRUCTION SET P83CL882 The asynchronous 80C51 family uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes power consumption in idle and active modes as well as byte efficiency and execution speed. Typical execution times and energy consumption at room temperature (Tamb = 25 C) and VDD = 3.0 V are given in Table 78. Remark: For most opcodes the numbers for execution speed and energy are also strongly dependent on the data (ADD, SUBB, DEC, INC, MUL, DIV, DA conditional jumps etc.) and the operand address (CPU internal SFRs or SFRs in a peripheral block). Table 78 Instruction set MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A, Rn A, direct A, @ Ri A, #data A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A add register to A add direct byte to A add indirect RAM to A add immediate data to A add register to A with carry flag add direct byte to A with carry flag add indirect RAM to A with carry flag add immediate data to A with carry flag subtract register from A with borrow subtract direct byte from A with borrow subtract indirect RAM from A with borrow subtract immediate data from A with borrow increment A increment register increment direct byte increment indirect RAM decrement A decrement register decrement direct byte decrement indirect RAM increment data pointer multiply A and B divide A by B decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 0.20 0.24 0.21 0.23 0.20 0.25 0.21 0.23 0.20 0.24 0.21 0.23 0.17 0.18 0.22 0.19 0.17 0.18 0.22 0.19 0.15 0.15 0.73 0.17 1.13 1.68 1.36 1.40 1.14 1.68 1.37 1.45 1.13 1.69 1.36 1.43 0.79 1.16 1.75 1.35 0.81 1.17 1.75 1.38 0.78 0.70 3.58 0.74 2* 25 26 and 27 24 3* 35 36 and 37 34 9* 95 96 and 97 94 04 0* 05 06 and 07 14 1* 15 16 and 17 A3 A4 84 D4 DESCRIPTION EXEC. ENERGY(1) BYTES TIME(1) (nJ) (s) OPCODE (HEX) Logic operations ANL ANL ANL ANL A, Rn A, direct A, @Ri A, #data AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A 1 2 1 2 0.20 0.30 0.21 0.23 1.24 1.91 1.44 1.50 5* 55 56 and 57 54 2001 Jun 19 66 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 MNEMONIC ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A A A A A A DESCRIPTION AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte exclusive-OR register to A exclusive-OR direct byte to A exclusive-OR indirect RAM to A exclusive-OR immediate data to A exclusive-OR A to direct byte exclusive-OR immediate data to direct byte clear A complement A rotate A left rotate A left through the carry flag rotate A right rotate A right through the carry flag swap nibbles within A EXEC. ENERGY(1) BYTES TIME(1) (nJ) (s) 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 0.26 0.28 0.29 0.29 0.19 0.21 0.24 0.27 0.29 0.29 0.19 0.21 0.24 0.27 0.14 0.15 0.15 0.15 0.17 0.15 0.14 1.96 2.41 1.71 1.72 1.27 1.23 1.78 2.16 1.72 1.72 1.31 1.33 1.83 2.27 0.71 0.93 0.73 0.74 0.82 0.73 0.71 OPCODE (HEX) 52 53 4* 45 46 and 47 44 42 43 6* 65 66 and 67 64 62 63 E4 F4 23 33 03 13 C4 Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data @RI, A @Ri, direct @Ri, #data DPTR, #data 16 move register to A move direct byte to A move indirect RAM to A move immediate data to A move A to register move direct byte to register move immediate data to register move A to direct byte move register to direct byte move direct byte to direct byte move indirect RAM to direct byte move immediate data to direct byte move A to indirect RAM move direct byte to indirect RAM move immediate data to indirect RAM load data pointer with a 16-bit constant 1 2 1 2 1 2 2 2 2 3 2 3 1 2 3 3 0.15 0.19 0.16 0.21 0.13 0.23 0.16 0.18 0.21 0.25 0.22 0.21 0.14 0.25 0.11 0.20 0.89 1.49 1.13 1.85 0.86 1.90 1.28 1.47 1.68 2.22 1.92 1.85 1.01 2.09 0.92 1.58 E* E5 E6 and E7 74 F* A* 7* F5 8* 85 86 and 87 75 F6 and F7 A6 and A7 76 and 77 90 2001 Jun 19 67 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 MNEMONIC MOVC MOVC DESCRIPTION EXEC. ENERGY(1) BYTES TIME(1) (nJ) (s) 1 1 1 1 1 1 2 2 1 2 1 1 0.31 0.32 - - - - 0.26 0.26 0.20 0.25 0.21 0.19 2.34 2.47 - - - - 1.62 1.66 1.35 1.98 1.42 1.38 OPCODE (HEX) 93 83 E2 and E3 E0 F2 and F3 F0 C0 D0 C* C5 C6 and C7 D6 and D7 A, @A + DPTR move code byte relative to DPTR to A A, @A + PC move code byte relative to PC to A move external RAM (8-bit address) to A move external RAM (16-bit address) to A move A to external RAM (8-bit address) move A to external RAM (16-bit address) push direct byte onto stack pop direct byte from stack exchange register with A exchange direct byte with A exchange indirect RAM with A exchange LOW-order nibble indirect RAM with A MOVX(2) A, @Ri MOVX(2) A, @DPTR MOVX(2) PUSH POP XCH XCH XCH XCHD @Ri, A direct direct A, Rn A, direct A, @Ri A, @Ri MOVX(2) @DPTR,A Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C clear carry flag clear direct bit set carry flag set direct bit complement carry flag complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag move direct bit to carry flag move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 0.11 0.24 0.11 0.24 0.12 0.23 0.21 0.23 0.21 0.23 0.22 0.24 0.64 1.51 0.65 1.71 0.68 1.59 1.30 1.55 1.33 1.54 1.34 1.52 C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 addr 12 22 32 1 addr 02 80 73 60 70 40 50 Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC addr11 addr16 rel @A+DPTR rel rel rel rel addr11 addr16 absolute subroutine call long subroutine call return from subroutine return from interrupt absolute jump long jump short jump (relative address) jump indirect relative to the DPTR jump if A is zero jump if A is not zero jump if carry flag is set jump if carry flag is not set 68 2 3 1 1 2 3 2 1 2 2 2 2 0.40 0.45 0.20 0.43 0.29 0.32 0.26 0.46 0.29 0.26 0.24 0.29 2.64 3.09 1.03 3.01 1.76 2.14 1.50 2.63 1.62 1.34 1.23 1.61 2001 Jun 19 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 MNEMONIC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP Notes 1. Verified on sampling base. bit, rel bit, rel bit, rel A, direct, rel A, #data, rel Rn, #data, rel Ri, #data, rel Rn, rel direct, rel DESCRIPTION jump if direct bit is set jump if direct bit is not set jump if direct bit is set and clear bit compare direct to A and jump if not equal compare immediate to A and jump if not equal compare immediate to register and jump if not equal compare immediate to indirect and jump if not equal decrement register and jump if not zero decrement direct and jump if not zero no operation EXEC. ENERGY(1) BYTES TIME(1) (nJ) (s) 3 3 3 3 3 3 3 2 3 1 0.31 0.36 0.36 0.34 0.35 0.35 0.36 0.33 0.39 0.11 1.90 2.29 2.25 2.27 2.38 2.59 2.82 2.29 2.89 0.63 OPCODE (HEX) 20 30 10 B5 B4 B* B6 and B7 D* D5 00 2. Only applicable if XRAM is present on-chip (no external access possible). Table 79 Notation for data addressing modes SYMBOL Rn direct Ri #data #data 16 bit addr16 addr11 rel working registers R0 to R7 128 internal RAM locations and any special function register (SFR) indirect internal RAM location addressed by register R0 or R1 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction direct addressed bit in internal RAM or SFR 16-bit destination address; used by LCALL and LJMP; the branch will be anywhere within the 64 kbytes program memory address space 11-bit destination address; used by ACALL and AJMP. The branch will be within the same 2-kbyte page of program memory as the first byte of the following instruction signed (two's complement) 8-bit offset byte; used by SJMP and all conditional jumps; range is -128 to +127 bytes relative to first byte of the following instruction DESCRIPTION Table 80 Hexadecimal opcode cross-reference SYMBOL * * 8, 9, A, B, C, D, E and F 11, 31, 51, 71, 91, B1, D1 and F1 01, 21, 41, 61, 81, A1, C1 and E1 DESCRIPTION 2001 Jun 19 69 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... andbook, full pagewidth 2001 Jun 19 70 7.1 Philips Semiconductors first hexadecimal character of opcode second hexadecimal character of opcode 6 INC direct DEC direct ADD A,direct ADDC A,direct ORL A,direct ANL A,direct XRL A,direct INC@Ri 0 DEC@Ri 0 ADD A,@Ri 0 ADDC A,@Ri 0 ORL A,@Ri 0 ANL A,@Ri 0 XRL A,@Ri 0 MOV @Ri,#data 0 MOV direct,@Ri 0 SUBB A,@Ri 0 MOV @Ri,direct 0 CJNE A,direct,rel XCH A,direct DJNZ direct,rel MOV * A,direct MOV direct,A CJNE @Ri,#data,rel 0 XCH A,@Ri 0 XCHD A,@Ri 0 MOV A,@Ri 0 MOV @Ri,A 0 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 1 0 1 2 7 8 9 A B C D E F 80C51 Ultra Low Power (ULP) telephony controller Instruction map 0 0 NOP JBC bit,rel JB bit,rel JNB bit,rel JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DPTR,#data 16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DPTR MOVX @DPTR,A 1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 2 LJMP addr16 LCALL addr16 RET 3 RR A RRC A RL A RLC A ORL direct,#data ANL direct,#data XRL direct,#data JMP @A+DPTR MOVC A,@A+PC MOVC A,@A+DPTR INC DPTR CPL C CLR C SETB C 4 INC A DEC A ADD A,#data ADDC A,#data ORL A,#data ANL A,#data XRL A,#data MOV A,#data DIV AB SUBB A,#data MUL AB CJNE A,#data,rel SWAP A DA A CLR A CPL A 5 INC Rn 3 4 5 6 7 1 DEC Rn 3 4 5 6 7 2 ADD A,Rn 3 4 5 6 7 3 ADDC A,Rn 3 4 5 6 7 RETI ORL direct,A ANL direct,A XRL direct,A ORL C,bit ANL C,bit MOV bit,C MOV C,bit CPL bit CLR bit SETB bit MOVX A,@Ri 1 MOVX @Ri,A 0 1 4 ORL A,Rn 3 4 5 6 7 5 ANL A,Rn 3 4 5 6 7 6 XRL A,Rn 3 4 5 6 7 7 MOV direct,#data MOV direct,direct SUBB A,direct MOV Rn,#data 3 4 5 6 7 8 MOV direct,Rn 3 4 5 6 6 7 7 9 A SUBB A, Rn 3 4 5 MOV Rn,direct 3 4 5 6 7 B CJNE Rn,#data,rel 2 3 4 5 6 7 C XCH A,Rn 3 4 5 6 7 D DJNZ Rn,rel 3 4 5 6 7 E MOV A,Rn Product specification P83CL882 0 3 4 5 6 7 F MGL457 MOV Rn,A 3 4 5 6 7 * MOV A, ACC is not a valid instruction. Fig.33 Instruction map. Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 8 8.1 APPLICATION INFORMATION Introduction P83CL882 * The CPU itself does not need a clock for code execution * The performance (MIPs) is not dependent on oscillator frequency but strongly related to VDD, temperature, silicon parameters and type of software. It always runs at the maximum speed determined by the external influences above. Therefore, it operates also with the maximum power consumption in the minimum time. Generally the lower the temperature and the higher the VDD the faster the CPU runs. Details on instruction speed and energy consumption per instruction can be found in Chapter 7. Because of the above mentioned properties some hints are given for using this controller in any kind of application in an efficient way. * Due to the high CPU performance, independent of clock frequency, certain functions (e.g. serial or customized interfaces) can be built in software in a very efficient and flexible way. * In classic 80C51 software the user (software engineer) was able to rely on cycle-timing for wait-loops, synchronisation in the system or similar usage (e.g. NOP instruction for waiting one machine cycle). When using the asynchronous CPU wait-loops should be implemented by starting a timer and putting the CPU in Idle mode in order to wait for an interrupt. Significant power reduction and a much more robust software will be obtained. If in an application the instruction counter is needed Timer 0 or 1 can be used with the instruction request signal connected to the clock source input. * One should avoid using `wait-until'-loops (SFR polling). This would lead to maximum CPU-load resulting in very high current consumption. The CPU should always be used as an event driven machine waiting for interrupts. After an activity the device must be entered in Idle or Power-down mode as fast as possible, the current is then reduced down to leakage. The device provides flexible means (interrupts, timer, counters) for a recovery from these power reduction modes. This chapter presents some information about how to use the P83CL882 in an application. It is not intended to replace the application notes but serves as a quick help when starting to work with the Philips Ultra Low Power handshake microcontrollers. There are some important improvements between the silicon in plastic packages and the Metalink EH emulator system which are described here. Furthermore, some hints on software development and power consumption are given to help the user take advantage of the full benefits of the handshake CPU. 8.2 Differences between P83CL882 and the Metalink EH emulation system * The SYSCON SFR does not exist on the emulator system * On the emulator the oscillator can only be used in normal mode which is the default start-up mode of the P83CL882. The hysteresis input comparator does not exist * The clock source of the Timer 0 and 1 is always fpsc on the emulator system. The timers can be used as counters, counting from external pin T1 or T0 but this is not possible in Power-down mode. * The interrupts T0 and T1 can cause on the emulator only a wake-up from idle and not from power-down * Prescaler bits PRESC[7:5] are not available on the emulator; therefore the synchronous mode and clock out functionality is not present * MSK polarity cannot be inverted on the emulator * INT1 interrupt is on the emulator version present on P3.3 where it is mapped on P3.1 on the P83CL882 * The clock output on P1.4 does not exist on the emulator. 8.3 The asynchronous handshake CPU As the CPU of the P83CL882 is built in asynchronous technology (hand-shake mechanism) some properties are singular to it in comparison to standard synchronous 80C51 controllers: 2001 Jun 19 71 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 9 9.1 HOW TO ESTIMATE P83CL882 POWER CONSUMPTION General P83CL882 In this mode the power consumption is only dependent on outside activity (port toggling, gate-current) and leakage (see Fig.34). 9.2.2 IDLE MODE Due to the use of the Philips unique asynchronous technology within the CPU, the power estimation must be done by taking into account several circumstances. To have an accurate power estimation the application must be well known. This especially means that all (or the most significant) application modes (e.g. idle or operation modes) are known and their weight or contribution - what is done when with which occurrence - can be estimated precise enough. 9.2 9.2.1 Modes POWER-DOWN MODE In Idle mode the oscillator (if enabled), the clock tree and the enabled peripheral functions are running. The peripheral functions are fixed to the peripheral clock (fper or fpsc). In Figs 39, 39 and 39 one can see the behaviour of the idle current with no peripheral functions switched on. 9.2.3 OPERATING MODE In Power-down there is no circuitry active which is drawing current. The CPU, the oscillator, the clock tree and the peripheral functions are switched off except Timer 0 and 1 which can function as counter in Power-down mode. The device can be woken-up by an interrupt. 9.3 Examples of power consumption estimation In operating mode the CPU, the oscillator, the clock tree and the enabled peripheral functions are running. While the peripheral functions are fixed to the peripheral clock (fper or fpsc) the CPU is completely free running. In plain words: it does one instruction after the other without any clocking nor timing scheme. In addition to that and to make code execution faster following instruction is pre-fetched while an instruction is being executed. A rough estimation of device power consumption can be made by an add-up of the Power-down mode current, Idle mode current, enabled peripheral function(s) current and estimated CPU processing load times mean value of operating current: IDD(pd) + IDD(id) + Iperiphery + CPU load x IDD(op). Assume an application part where the device is 50% in idle, during idle for total 40% a peripheral function is running, for 20% the CPU is active and the rest is power-down state. Then the averaged power consumption can roughly be calculated as follows: Iaverage = (100% x IDD(pd)) + (50% x IDD(id)) + (40% x Iperiphery) + (20% x IDD(op)). When the number of instructions within an application part and its execution time is known, then the CPU processing load can be estimated as shown below. The CPU performance (in Mips) is given by the supply voltage: number of instructions 10 CPU processing load = 100% x ---------------------------------------------------------- x ----------------------------------------------------------------------CPU performance (in Mips) time (seconds) -6 2001 Jun 19 72 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 9.3.1 EXAMPLE OF RING-DETECTION P83CL882 Typically a ring-detection is done by a time measurement using a timer. The device is activated by an external interrupt (e.g. AC on the A/B line), the oscillator runs up and the device carries out the time measurement with a timer. In this example it can be assumed that to read the timer contents, decide whether an external ringer should be enabled or not, to restart the timer and then go into Idle mode is around 30 instructions. Assuming a ringing frequency of about 25 Hz and a device supply voltage of 3.0 V this gives a CPU performance of about 4.5 Mips. 100% x 30 instructions x 25 Hz The CPU processing load is then: --------------------------------------------------------------------------------- 0.017% 4.5 Mips x 1000000 From the calculation above it can be seen that the idle current will be dominant in this application part. A/B line Activity IDLE IDLE IDLE IDLE IDLE IDLE CPU operation MGT314 Fig.34 Ring-detection sequence. 2001 Jun 19 73 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 10 LIMITING VALUES According to the Absolute Maximum Ratings System (IEC 60134); note 1. SYMBOL VDD VI II/O IDD Ves Ptot Tstg Tamb Notes supply voltage input voltage maximum sink/source current for each input/output pin maximum supply current for any supply pin electrostatic handling voltage total power dissipation storage temperature operating ambient temperature (for all devices) machine model; note 4 note 2 PARAMETER CONDITIONS MIN. -0.5 -0.5 - - human body model; note 3 - - - -55 -25 P83CL882 MAX. +4.6 10 50 2000 175 100 +125 +70 UNIT V mA mA V V mW C C VDD + 0.5 V 1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise specified. 2. May not exceed the limiting value for VDD. 3. According to SNW-FQ-302A: C = 100 pF; R = 1.5 kW. 4. According to SNW-FQ-302B: C = 200 pF; L = 0.75 mH. 2001 Jun 19 74 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 11 CHARACTERISTICS VDD = 1.8 to 3.6 V; VSS = 0 V; fxtal = 4 MHz; Tamb = -25 to +70 C; unless otherwise specified. SYMBOL Supply VDD supply voltage operating RAM data retention IDD operating supply current VDD = 3 V; Tamb = 25 C; at 100% CPU load note 3 notes 4 and 5 IDD(id) supply current Idle mode VDD = 3 V; external clock; note 6 VDD = 3 V; Tamb = 25 C; crystal connected; note 5 IDD(pd) supply current Power-down mode VDD = 3 V; Tamb = 25 C; note 7 VDD = 3 V; Tamb = 70 C; note 7 IDD(block) supply current per block: MSK modem Watchdog Timer I2C-bus Timer 2 Timer 0 or 1 Performance fXTAL1 CPUperf external clock input frequency CPU performance notes 5 and 9 Tamb = 25 C; notes 4 and 5 VDD = 1.8 V VDD = 3.0 V CPUeff CPU efficiency Tamb = 25 C; notes 4 and 5 VDD = 1.8 V VDD = 3.0 V - - 1910 555 - - 2.6 4.5 DC - VDD = 3 V; Tamb = 25 C; note 8 - - - - - 14 2 30 4 10 - - - - - 3.0 60 300 1.8(2) 1.0 - - PARAMETER CONDITIONS MIN. TYP. P83CL882 MAX.(1) UNIT 3.6 3.6 V V 4.5 - 75 - mA mA A A - - 0.1 - - 4.5 A A - - - - - 12 A A A A A MHz - - Mips Mips - - Mips/W Mips/W 2001 Jun 19 75 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 SYMBOL PARAMETER CONDITIONS MIN. - - TYP. MAX.(1) UNIT Inputs (Ports, MIN and RST) VIL VIH IIL IIL(T) LOW-level input voltage HIGH-level input voltage LOW-level input current; ports in standard port configuration LOW-level input current; HIGH-to-LOW transition; ports in standard port configuration input leakage current; ports in open-drain or high-impedance input configuration notes 10 and 11 note 10 VIN = 0.4 V; note 12; see Fig.44 VIN = 0.5VDD; note 12; see Fig.44 VSS VI VDD 0 0.8VDD - - 0.2VDD VDD 50 1000 V V A A 20 200 ILI - - 100 nA Outputs (Ports and RST) IOL IOH LOW-level output current; except SDA and SCL; note 12 HIGH -level output current; push-pull configuration only VDD = 3.0 V; VOL = 0.4 V VDD = 3.0 V; VOL = 1.5 V VDD = 3 V; VOH = VDD - 0.4 V VDD = 3 V; VOH = VDD - 1.5 V IRST RST pull-up resistor current VDD = 3 V; VOH = VDD - 0.4 V VDD = 3 V; VOH = VSS Amplitude Controlled Oscillator (ACO) fosc Rfb gm Ci(L)(XTAL1) VXTAL1(p-p) oscillator frequency feedback resistance transconductance capacitive input load on XTAL1 external clock signal amplitude on pin XTAL1 (peak-to-peak value) mean value of external clock signal LOW-level input voltage pin XTAL1 HIGH-level input voltage pin XTAL1 external required load capacitance on XTAL1 and XTAL2 in oscillator mode notes 5 and 9 note 5 Tamb = 25 C; VDD = 1.8 V Tamb = 25 C; VDD = 3 V 1 - 1.0 3.0 - 0.4VDD - 200 - - 500 - 12 - 2.5 6 1000 VDD MHz k mS mS fF V 4 - 4 - 0.05 - - 10 - 10 0.1 0.3 - - - - - 2.5 mA mA mA mA A A VDC(XTAL1) VIL(XTAL1) VIH(XTAL1) C1e,C2e in oscillator mode in external clock mode in external clock mode - 0 0.6VDD - 0.5VDD - - 22 - 0.2VDD VDD - V V V pF 2001 Jun 19 76 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller Notes P83CL882 1. The measurement of the maximum value is done with all output pins disconnected; VIL = VSS; VIH = VDD; RST = VDD; XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled. To see the typical value of each instruction please consult Table 78 "Instruction set". 2. The minimum operating voltage is the level where VDD is higher than the power-on reset level. 3. For this measurement an instruction was selected which current consumption is around the typical value; the instruction is: LJMP to ADDR + 03H. 4. The typical operating supply current is evaluated as a mean value over all possible instructions (100% CPU load) and with a crystal connected. 5. Verified on sampling basis. 6. The Idle mode supply current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD; XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled. 7. The Power-down mode supply current is measured with all output pins and RST disconnected; VIL = VSS; VIH = VDD; XTAL1 and XTAL2 not connected. 8. The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller, the current consumption of the CPU weighted with the processing must be added. Example: the typical average current consumption of the microcontroller in operating mode with 10% CPU processing load, Watchdog timer and MSK active can be calculated as: 10% x ICPU + IDD(id) + IWD + IMSK. 9. For some peripheral blocks it could be required to reduce the internal clock frequency with the PSC2 and an additional divider inside the peripherals. Symbol `fXTAL1' is meant for external device clocking and `fosc' is meant as on-chip oscillator frequency. 10. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1. 11. Not valid for pins SDA, SCL, RST and MIN. 12. Due to the maximum allowed current, the number of output pins switching at the same time should be limited to one. 2001 Jun 19 77 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 MGW040 handbook, halfpage 5 MGW041 handbook, halfpage 5 MIPS 4 MIPS 4 3 3 2 2 1 1 0 1.5 2 2.5 3 3.5 VDD (V) 4 0 -50 -25 0 25 50 75 100 Tamb (C) Fig.35 Typical CPU performance as a function of VDD, Tamb = 25 C (mean value over all instructions). Fig.36 Typical CPU performance as a function of Tamb, VDD = 3 V (mean value over all instructions). MGW042 handbook, halfpage 2000 MGW043 handbook, halfpage 5 MIPS/W 1600 I DD (mA) 4 1200 3 800 2 400 1 0 1.5 2 2.5 3 3.5 VDD (V) 4 0 1.5 2 2.5 3 3.5 VDD (V) 4 Fig.37 Typical CPU efficiency as a function of VDD, Tamb = 25 C (mean value over all instructions). Fig.38 Typical operating current as a function of VDD, Tamb = 25 C; 100% CPU load (mean value over all instructions). 2001 Jun 19 78 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 MGW044 handbook, halfpage 4 handbook, halfpage 400 MGW045 I DD (mA) 3 I DD (A) 300 2 200 1 100 0 -50 -25 0 25 50 75 Tamb (C) 100 0 1.5 2 2.5 3 3.5 VDD (V) 4 Fig.39 Typical operating current as a function of Tamb, VDD = 3.0 V; 100% CPU load (mean value over all instructions). Fig.40 Typical Idle current as a function of VDD, Tamb = 25 C; fosc = 4 MHz (crystal). MGW046 handbook, halfpage 400 handbook, halfpage 400 MGW047 I DD (A) 300 I DD (A) 300 200 200 100 100 0 -50 -25 0 25 50 75 Tamb (C) 100 0 0 2 4 6 8 10 12 f osc (MHz) Fig.41 Typical Idle current as a function of Tamb, VDD = 3.0 V; fosc = 4 MHz (crystal). Fig.42 Typical Idle current as a function of oscillator (crystal) frequency, VDD = 3.0 V; Tamb = 25 C. 2001 Jun 19 79 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller P83CL882 4 I DD(pd) (A) 3 MBL262 2 1 (1) (2) 0 0 (1) Tamb = 70 C (2) Tamb = 25 C 1 2 3 VDD (V) 4 Fig.43 Typical Power-down current as a function of VDD. handbook, full pagewidth 500 A MGL506 II I IL(T) 10 A 0 IIL 0.3VDD 0.5VDD VDD Fig.44 Port input current. 2001 Jun 19 80 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 12 PACKAGE OUTLINE TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm P83CL882 SOT487-1 D E A X c y HE vMA Z 32 17 A2 A1 pin 1 index Lp L (A 3) A 1 e 16 bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.10 10.90 E(2) 6.20 6.00 e 0.65 HE 8.30 7.90 L 1.00 Lp 0.75 0.50 v 0.20 w 0.10 y 0.10 Z 0.78 0.48 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT487-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 99-12-27 2001 Jun 19 81 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 13 SOLDERING 13.1 Introduction to soldering surface mount packages P83CL882 If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2001 Jun 19 82 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods P83CL882 SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2001 Jun 19 83 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 14 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS P83CL882 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 15 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2001 Jun 19 84 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller 17 PURCHASE OF PHILIPS I2C COMPONENTS P83CL882 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Jun 19 85 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller NOTES P83CL882 2001 Jun 19 86 Philips Semiconductors Product specification 80C51 Ultra Low Power (ULP) telephony controller NOTES P83CL882 2001 Jun 19 87 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001 Internet: http://www.semiconductors.philips.com SCA 72 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/01/pp88 Date of release: 2001 Jun 19 Document order number: 9397 750 07598 |
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